2015 IEEE 17th Electronics Packaging and Technology Conference (EPTC)最新文献_第7页

3D package failure analysis challenge and solution 3D封装失效分析挑战及解决方案

2015 IEEE 17th Electronics Packaging and Technology Conference (EPTC) Pub Date : 2015-12-01 DOI: 10.1109/EPTC.2015.7412374

F. Chao, Li Xiaomin, J. Kow

引用次数: 2

Creep behavior of Innolot solder alloy using small lap-shear specimens 用小弯剪试样研究银诺焊料合金的蠕变行为

2015 IEEE 17th Electronics Packaging and Technology Conference (EPTC) Pub Date : 2015-12-01 DOI: 10.1109/EPTC.2015.7412360

Q. Tao, L. Benabou, K. Tan, J. Morelle, F. Ben Ouezdou

引用次数: 14

Enabling pre-assembly process of 3D wafers with high topography at the backside 实现背面高形貌3D晶圆的预组装工艺

2015 IEEE 17th Electronics Packaging and Technology Conference (EPTC) Pub Date : 2015-12-01 DOI: 10.1109/EPTC.2015.7412326

A. Podpod, C. Demeurisse, F. Inoue, F. Duval, J. Visker, J. de Vos, K. Rebibis, R. A. Miller, G. Beyer, E. Beyne

引用次数: 0

Ultra slim packaging and assembly method for 360-μm diameter guide wires 直径360 μm导线的超薄封装组装方法

2015 IEEE 17th Electronics Packaging and Technology Conference (EPTC) Pub Date : 2015-12-01 DOI: 10.1109/EPTC.2015.7727915

Ramona B. Damalerio, E. L. Tan, K. Tan, Ruiqi Lim, Weiguo Chen, Ming-Yuan Cheng

{"title":"Ultra slim packaging and assembly method for 360-μm diameter guide wires","authors":"Ramona B. Damalerio, E. L. Tan, K. Tan, Ruiqi Lim, Weiguo Chen, Ming-Yuan Cheng","doi":"10.1109/EPTC.2015.7727915","DOIUrl":"https://doi.org/10.1109/EPTC.2015.7727915","url":null,"abstract":"In this work, we present an ultra-slim profile packaging and assembly solution of a 360-μm diameter medical guide wire fitted and integrated with silicon based fractional flow reserve (FFR) sensor. The miniaturization of the whole sensorized guide wire assembly without sacrificing its sensing functionality was made possible by the use of polyimide flexible printed circuit board (FPCB) as the substrate material for the silicon platform and by the use of lowest possible wire looping profile to create interconnection between the FFR sensor and the FPCB's bonding pads using the gold wires. In order to reinforce and protect the wire interfaces, as well as to maintain the required biocompatibility of the whole system, a thin layer of Polydimethylsiloxane (PDMS) was used for the encapsulation process. Long signal wires were then attached to the bonding pads of FPCB before finally fitted inside a miniaturized metal housing. This whole system has easily fit and integrated with the 360-μm diameter medical guide wire. In order to verify the packaging feasibility, the electrical short testing of the bonding pads and SEM observations were conducted.","PeriodicalId":418705,"journal":{"name":"2015 IEEE 17th Electronics Packaging and Technology Conference (EPTC)","volume":"38 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126914343","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 1

Effect of impact force towards Cu wire bonding reliability 冲击力对铜丝键合可靠性的影响

2015 IEEE 17th Electronics Packaging and Technology Conference (EPTC) Pub Date : 2015-12-01 DOI: 10.1109/EPTC.2015.7412425

L. Chia, Chua Kok Yau, Tan Chee

{"title":"Effect of impact force towards Cu wire bonding reliability","authors":"L. Chia, Chua Kok Yau, Tan Chee","doi":"10.1109/EPTC.2015.7412425","DOIUrl":"https://doi.org/10.1109/EPTC.2015.7412425","url":null,"abstract":"Copper (Cu) wire bonding technology is now widely held in mass production of semiconductor industry. The main benefit is cost advantage against Au wire and secondly enhance product performance and reliability. More new products are design in with Cu wire bonding and new wire bonding machine also equipped with Cu wire bonding capability. The market trend shows acceptance of Cu wire bonding products increasing yearly. Thus, Cu wire become the most accepted interconnect material besides Au & Al wire. However Cu wire property - hardness, is one of the key challenges for wire bonding process. This lead to a more narrow process window compare to Au wire and lead to more reliability risk. To overcome the Cu wire bonding challenge many researches been carried out. From material aspect, softer Cu wire, robust bond pad, etc. are developed to enhance the process ability. From process aspect, multi-steps bonding is the preferred solution. Multi-steps bonding segmented bonding into impact stage and bonding stage. The impact stage is the first contact of the FAB to the bond pad, which is crucial to form the ball size, ball height and bond pad cratering defect. The bonding stage determines the integrity of bonding. This paper presents how the impact force can influence the product reliability. To determine the impact force experience by bond pad during bond a load cell is being used to measure actual impact force. Different impact force by varying the machine setting, the output response is the Al remnant thickness and cratering result. Kim et al. [1] reported reaction rate of Cu/Al IMC formation was obtained using the Arrhenius plot (lnK versus 1/T) and therefore the theoretical IMC thickness can be calculated as a function of time and temperature. Using the theoretical model a minimum Al remnant thickness at zero hour can be target in order for the Cu/Al interface to withstand the thermal reliability stress. Ultimately, optimum setting for impact stage and bonding stage can be identified for a robust bonding.","PeriodicalId":418705,"journal":{"name":"2015 IEEE 17th Electronics Packaging and Technology Conference (EPTC)","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124466277","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 2

Study on ultra low loop copper wire bonding process using 0.8mils Cu wire for low profile package applications 低规格封装用0.8mils铜线超低环铜线粘接工艺研究

2015 IEEE 17th Electronics Packaging and Technology Conference (EPTC) Pub Date : 2015-12-01 DOI: 10.1109/EPTC.2015.7412423

Norhanani Binte Jaafar, Eva Wai Leong Ching

{"title":"Study on ultra low loop copper wire bonding process using 0.8mils Cu wire for low profile package applications","authors":"Norhanani Binte Jaafar, Eva Wai Leong Ching","doi":"10.1109/EPTC.2015.7412423","DOIUrl":"https://doi.org/10.1109/EPTC.2015.7412423","url":null,"abstract":"In recent years, as IC packaging development has moved towards higher power, smaller size, thinner dimensions, denser circuits and higher reliability, wire bonding is still the most commonly used bonding interconnection technique in first level microelectronic packages [1]. Gold wire is usually used for bonding to connect the chip and lead frame/substrate metallization because of its easy handling and strong bond with the bond pad metal. However, recently copper wire emerged as an alternative to gold wire due to mainly huge merit in cost saving, higher electrical and thermal conductivities than gold wire, which will contribute to higher signal speed, less heat generation and better heat dissipation[2]. Copper wire has been used in low pin count ICs, high pin count products and stacked die. In high I/O applications, copper wire with smaller diameter is required and wire sweep performance is critical as even small wire sweep may cause wire short. Wire short can be prevented with having low loop height specification for the high I/O application and to achieve thinner and smaller packaging. In this paper, heat-affected zone (HAZ) for three types of Cu wire material of 0.8mils wire diameter were studied to achieve the ultra-low loop height range of 75.0μm. The ultra-low loop wire bonding process optimization for three different Cu wires and bond quality were assessed. The advantages and disadvantages of individual 0.8mils Cu wire types were discussed by comparing the wire pull measurements for three types of 0.8mils Cu wire. The surface of silicon chip after bonding was checked to confirm whether peeling or crack on bond pad surface occurred after the wire pull test for each wire types using high power optical microscope.","PeriodicalId":418705,"journal":{"name":"2015 IEEE 17th Electronics Packaging and Technology Conference (EPTC)","volume":"182 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121688013","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 1

Effect of third element addition on joint strength of low-Ag lead-free solder 添加第三元素对低银无铅焊料接头强度的影响

2015 IEEE 17th Electronics Packaging and Technology Conference (EPTC) Pub Date : 2015-12-01 DOI: 10.1109/EPTC.2015.7412283

Kyosuke Kobayashi, I. Shohji, M. Yamashita

{"title":"Effect of third element addition on joint strength of low-Ag lead-free solder","authors":"Kyosuke Kobayashi, I. Shohji, M. Yamashita","doi":"10.1109/EPTC.2015.7412283","DOIUrl":"https://doi.org/10.1109/EPTC.2015.7412283","url":null,"abstract":"Effects of additions of small amount of Bi, Ni and Ge in Sn-1.0Ag-0.7Cu (mass%) low-Ag lead-free solder on the strength and microstructure of the solder ball joint were investigated for Cu and electroless Ni-P/immersion Au (ENIG) electrodes. In the case of the Cu electrode, Cu6Sn5 and Cu3Sn layers form at the joint interfaces in the joints with Sn-1.0Ag-0.7Cu and Sn-1.0Ag-0.7Cu-2.0Bi (mass%). (Cu, Ni)6Sn5 and (Cu, Ni)3Sn layers form at the joint interfaces in the joints with Sn-1.0Ag-0.7Cu-0.07Ni-0.01Ge (masss%) and Sn-1.0Ag-0.7Cu-2.0Bi-0.07Ni-0.01Ge (mass%). In the ball shear test at a low shear speed of 0.001 m/s, fracture mainly occurs in solder and the addition of Bi is effective to improve ball shear force. Similar tendency was observed in the joints with ENIG electrodes. In the ball shear test at a high shear speed of 1 m/s, the addition of Ni is effective to improve ball shear force. After aging at 120°C for 3 weeks, ball shear force in the joint with Sn-1.0Ag-0.7Cu-2.0Bi-0.07Ni-0.01Ge was excellent. In the case of the ENIG electrode, Ni-Sn-Cu phases form at the joint interfaces in all solder investigated. In the ball shear test at the high shear speed, the effect of added elements on ball shear force is negligible. Although IMC fracture mainly occurs in the joint with solder including Ni, the effect of IMC fracture on ball shear force is negligible. Furthermore, it was found that absorption energy in the ball shear test decreases when fracture occurs in the IMC layer regardless of the electrode type.","PeriodicalId":418705,"journal":{"name":"2015 IEEE 17th Electronics Packaging and Technology Conference (EPTC)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130612786","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Advanced wafer level technology: Enabling innovations in mobile, IoT and wearable electronics 先进的晶圆级技术:实现移动、物联网和可穿戴电子产品的创新

2015 IEEE 17th Electronics Packaging and Technology Conference (EPTC) Pub Date : 2015-12-01 DOI: 10.1109/EPTC.2015.7412320

S. Yoon, Boris Petrov, Kai Liu

{"title":"Advanced wafer level technology: Enabling innovations in mobile, IoT and wearable electronics","authors":"S. Yoon, Boris Petrov, Kai Liu","doi":"10.1109/EPTC.2015.7412320","DOIUrl":"https://doi.org/10.1109/EPTC.2015.7412320","url":null,"abstract":"New and emerging applications in the consumer and mobile space, the growing impact of the Internet of Things (IoT) and wearable electronics (WE), and the slowdown of Moore's law have been driving many new trends and innovations in advanced packaging technology. The semiconductor industry now has to focus on integration and system scaling to meet the ever-increasing electronic system demands for performance and functionality as well as the reduction of form factor, power consumption and cost. This paradigm shift from chip-scaling to system-scaling will reinvent microelectronics packaging, continue driving system bandwidth and performance, and help sustain Moore's Law. It also drives overall demand for maximum functional integration in the smallest and thinnest package with the lowest cost. The challenge for the semiconductor industry is to develop a disruptive packaging technology platform capable of achieving these goals. The most promising solutions in volume production today are advanced Wafer Level Packaging, such as Fan-out Wafer Level Packaging (FOWLP), embedded Wafer Level Ball Grid Array (eWLB) which provides significant bandwidth, performance, form factor and cost benefits compared to other packaging technologies available today. This article will discuss the wide range of FOWLP/eWLB adoptions and new features available for mobile, IoT and WE. This advanced technology is well designed for RF, MEMS/sensors, 3D SiP modules as well as thin, highly integrated packaging solutions. Innovative FOWLP/eWLB features will be also introduced with the merits and characterization data for specific applications.","PeriodicalId":418705,"journal":{"name":"2015 IEEE 17th Electronics Packaging and Technology Conference (EPTC)","volume":"14 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122279396","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 29

Modeling of the stick-slip effect in heavy copper wire bonding to determine and reduce tool wear 模拟重铜丝粘滑效应，以确定和减少刀具磨损

2015 IEEE 17th Electronics Packaging and Technology Conference (EPTC) Pub Date : 2015-12-01 DOI: 10.1109/EPTC.2015.7412375

A. Unger, W. Sextro, T. Meyer, Paul Eichwald, Simon Althoff, Florian Eacock, M. Brokelmann, M. Hunstig, K. Guth

{"title":"Modeling of the stick-slip effect in heavy copper wire bonding to determine and reduce tool wear","authors":"A. Unger, W. Sextro, T. Meyer, Paul Eichwald, Simon Althoff, Florian Eacock, M. Brokelmann, M. Hunstig, K. Guth","doi":"10.1109/EPTC.2015.7412375","DOIUrl":"https://doi.org/10.1109/EPTC.2015.7412375","url":null,"abstract":"To increase quality and reliability of copper wire bonds, self-optimization is a promising technique. For the implementation of self-optimization for ultrasonic heavy copper wire bonding machines, a model of stick-slip motion between tool and wire and between wire and substrate during the bonding process is essential. Investigations confirm that both of these contacts do indeed show stick-slip movement in each period oscillation. In a first step, this paper shows the importance of modeling the stick-slip effect by determining, monitoring and analyzing amplitudes and phase angles of tool tip, wire and substrate experimentally during bonding via laser measurements. In a second step, the paper presents a dynamic model which has been parameterized using an iterative numerical parameter identification method. This model includes Archard's wear approach in order to compute the lost volume of tool tip due to wear over the entire process time. A validation of the model by comparing measured and calculated amplitudes of tool tip and wire reveals high model quality. Then it is then possible to calculate the lifetime of the tool for different process parameters, i.e. values of normal force and ultrasonic voltage.","PeriodicalId":418705,"journal":{"name":"2015 IEEE 17th Electronics Packaging and Technology Conference (EPTC)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131006168","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 19

A method to form Si recess for Ge selective epitaxial growth using dry etch 一种利用干蚀刻形成用于锗选择性外延生长的硅凹槽的方法

2015 IEEE 17th Electronics Packaging and Technology Conference (EPTC) Pub Date : 2015-12-01 DOI: 10.1109/EPTC.2015.7412389

D. Wei, Song Junfeng

引用次数: 0