Enabling pre-assembly process of 3D wafers with high topography at the backside

Abstract

In a specific 3D die to die stacking scenario using a Si interposer technology for high band width interconnect applications1, wherein dies including the Silicon interposer were stacked first before placing it onto the substrate, posts a challenge on pre-assembly processes. This paper presents what and which areas the challenges are and reports on the solution found that enabled the pre-assembly processes for 3D wafers with high topography at the backside (Si interposer): a UV dicing tape that can handle the complexities at hand.