Study on ultra low loop copper wire bonding process using 0.8mils Cu wire for low profile package applications

Norhanani Binte Jaafar, Eva Wai Leong Ching
{"title":"Study on ultra low loop copper wire bonding process using 0.8mils Cu wire for low profile package applications","authors":"Norhanani Binte Jaafar, Eva Wai Leong Ching","doi":"10.1109/EPTC.2015.7412423","DOIUrl":null,"url":null,"abstract":"In recent years, as IC packaging development has moved towards higher power, smaller size, thinner dimensions, denser circuits and higher reliability, wire bonding is still the most commonly used bonding interconnection technique in first level microelectronic packages [1]. Gold wire is usually used for bonding to connect the chip and lead frame/substrate metallization because of its easy handling and strong bond with the bond pad metal. However, recently copper wire emerged as an alternative to gold wire due to mainly huge merit in cost saving, higher electrical and thermal conductivities than gold wire, which will contribute to higher signal speed, less heat generation and better heat dissipation[2]. Copper wire has been used in low pin count ICs, high pin count products and stacked die. In high I/O applications, copper wire with smaller diameter is required and wire sweep performance is critical as even small wire sweep may cause wire short. Wire short can be prevented with having low loop height specification for the high I/O application and to achieve thinner and smaller packaging. In this paper, heat-affected zone (HAZ) for three types of Cu wire material of 0.8mils wire diameter were studied to achieve the ultra-low loop height range of 75.0μm. The ultra-low loop wire bonding process optimization for three different Cu wires and bond quality were assessed. The advantages and disadvantages of individual 0.8mils Cu wire types were discussed by comparing the wire pull measurements for three types of 0.8mils Cu wire. The surface of silicon chip after bonding was checked to confirm whether peeling or crack on bond pad surface occurred after the wire pull test for each wire types using high power optical microscope.","PeriodicalId":418705,"journal":{"name":"2015 IEEE 17th Electronics Packaging and Technology Conference (EPTC)","volume":"182 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2015-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"1","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2015 IEEE 17th Electronics Packaging and Technology Conference (EPTC)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/EPTC.2015.7412423","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 1

Abstract

In recent years, as IC packaging development has moved towards higher power, smaller size, thinner dimensions, denser circuits and higher reliability, wire bonding is still the most commonly used bonding interconnection technique in first level microelectronic packages [1]. Gold wire is usually used for bonding to connect the chip and lead frame/substrate metallization because of its easy handling and strong bond with the bond pad metal. However, recently copper wire emerged as an alternative to gold wire due to mainly huge merit in cost saving, higher electrical and thermal conductivities than gold wire, which will contribute to higher signal speed, less heat generation and better heat dissipation[2]. Copper wire has been used in low pin count ICs, high pin count products and stacked die. In high I/O applications, copper wire with smaller diameter is required and wire sweep performance is critical as even small wire sweep may cause wire short. Wire short can be prevented with having low loop height specification for the high I/O application and to achieve thinner and smaller packaging. In this paper, heat-affected zone (HAZ) for three types of Cu wire material of 0.8mils wire diameter were studied to achieve the ultra-low loop height range of 75.0μm. The ultra-low loop wire bonding process optimization for three different Cu wires and bond quality were assessed. The advantages and disadvantages of individual 0.8mils Cu wire types were discussed by comparing the wire pull measurements for three types of 0.8mils Cu wire. The surface of silicon chip after bonding was checked to confirm whether peeling or crack on bond pad surface occurred after the wire pull test for each wire types using high power optical microscope.
低规格封装用0.8mils铜线超低环铜线粘接工艺研究
近年来,随着IC封装向着更高功率、更小尺寸、更薄尺寸、更密集电路和更高可靠性的方向发展,线键合仍然是一级微电子封装中最常用的键合互连技术[1]。金线通常用于连接芯片和引线框架/基板金属化,因为它易于操作并且与键垫金属结合牢固。然而,最近铜线作为金线的替代品出现,主要是由于铜线在成本节约方面的巨大优点,以及比金线更高的导电性和导热性,这将有助于更高的信号速度,更少的热量产生和更好的散热[2]。铜线已用于低引脚数集成电路,高引脚数产品和堆叠芯片。在高I/O应用中,需要更小直径的铜线,并且线扫描性能至关重要,因为即使很小的线扫描也可能导致线短。对于高I/O应用,可以通过具有低环路高度规格来防止线短,并实现更薄更小的封装。本文研究了三种线径为0.8mils的铜丝材料的热影响区(HAZ),实现了75.0μm的超低回路高度范围。对三种不同铜丝的超低环焊工艺优化及焊接质量进行了评价。通过对三种型号的0.8mils铜线的拉丝量的比较,讨论了各型号0.8mils铜线的优缺点。在高倍光学显微镜下对每一种线材进行拉丝试验后,检查粘接后的硅片表面,确认粘接垫表面是否出现剥离或裂纹。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
求助全文
约1分钟内获得全文 求助全文
来源期刊
自引率
0.00%
发文量
0
×
引用
GB/T 7714-2015
复制
MLA
复制
APA
复制
导出至
BibTeX EndNote RefMan NoteFirst NoteExpress
×
提示
您的信息不完整,为了账户安全,请先补充。
现在去补充
×
提示
您因"违规操作"
具体请查看互助需知
我知道了
×
提示
确定
请完成安全验证×
copy
已复制链接
快去分享给好友吧!
我知道了
右上角分享
点击右上角分享
0
联系我们:info@booksci.cn Book学术提供免费学术资源搜索服务,方便国内外学者检索中英文文献。致力于提供最便捷和优质的服务体验。 Copyright © 2023 布克学术 All rights reserved.
京ICP备2023020795号-1
ghs 京公网安备 11010802042870号
Book学术文献互助
Book学术文献互助群
群 号:481959085
Book学术官方微信