芯片封装上高性能系统的电流承载能力表征

N. Ying, Wong Wui Weng
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引用次数: 0

摘要

片上系统(SoC)技术正在从高功耗工作站迅速发展到低功耗平板电脑。由于复杂的SoC进一步集成了多种硬件功能,系统级片上架构正在成为功耗的重要来源。提高现有封装的载流能力(CCC)可能是以最低成本提高功耗的因素之一。为了解决当前SOC中典型的高引脚数有机衬底中焦耳加热的热效应,以不同的电流水平对测试车辆进行了通电,并测量了相应的温升。本文介绍了一种有效的载流容量表征方法来研究引脚支持更高电流水平的能力。它可以通过设置类似于应用条件的测试环境和挑战由保守方法定义的操作极限来实现。高载流能力提高了20%,这最终可以转化为具有复杂封装的当今SOC的性能和功率增益。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
Current carry capacity characterization for high performance system on chip packages
System on Chip (SoC) technology is rapidly evolved across high power workstations to low power tablets. As complex SoC further integrates several hardware functionalities, the system-level on-chip architecture is emerging as a significant source of power consumption. Improving current carry capacity (CCC) of existing packages can be one of factors to enhance power consumption with minimum cost. To deal with thermal effects of joule heating in a typical high pin count organic substrate of today SOC, a test vehicle was energized with various current levels and the correspondent temperature rise was measured. This paper introduces an effective current carry capacity characterization method to investigate the ability of pins to support higher current levels. It can be achieved by setting the test environment resembled to application conditions and to challenge operating limit which defined by a conservative approach. Up to 20% improvement in higher current carrying capacity was observed, which could ultimately translate into performance and power gain in today SOC with a complex package.
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