1997 Symposium on VLSI Technology最新文献

{"title":"0.25 /spl mu/m salicide CMOS Technology Thermally Stable Up To 1,000/spl deg/C With High TDDB Reliability","authors":"Ohguro, Yoshitomi, Morimoto, Harakawa, Momose, Katsumata, Iwai","doi":"10.1109/VLSIT.1997.623715","DOIUrl":"https://doi.org/10.1109/VLSIT.1997.623715","url":null,"abstract":"INTRODUCTION CoSi2 salicide technology is going to be used for 0.25 pm CMOS not only for the high speed digital application, but also for RF analog application, because of its low sheet resistance of the gate electrode without no 'narrow line effect'. Low gate resistance less than 5 QiU is indispensable for realizinglow noisefigureofless than 1dB ofanalogMOSFET [I]. IJsuaUy, the highest heat process after the CoSi2 salidde process has been less than 800 \"C. However, from the view point of future merged process with RF analog, logic and memory devices, it has been some times requested to use even higher temperature process to anneal capacitor dielectrics or to activate impurities after the salicide process. Thus, it is important to know the thermal stability of the CoSi2 resistance and TDDB reliability of the gate oxide with higher process temperature, for the CoSi2 process to be used in wide range of applications.","PeriodicalId":414778,"journal":{"name":"1997 Symposium on VLSI Technology","volume":"16 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-06-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115043533","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Highly Manufacturable 1Gb SDRAM","authors":"Lee, Nam, Park, Kim, Moon, Choi","doi":"10.1109/VLSIT.1997.623669","DOIUrl":"https://doi.org/10.1109/VLSIT.1997.623669","url":null,"abstract":"A fully working 1G SDRAM( 1073741824 bits) is fabricated by 0.18 pm CMOS technology. This is, to the best of our knowledge, the first fully working highest density DRAM ever achieved. By realizing fully working 1Gb SDRAM, the era of giga bit density is opened. The technologies employed in this 1Gb SDRAM are retrograded twin-well, STI, TiSi2 gate, Ta205+HSG capacitor, deep contact process, W-plug and W-wiring process followed by relaxed double metallization. In addition, the CMP process is also used for the global and local topography. In this study, the key items for realizing a fully working 1Gb SDRAM will be reported.","PeriodicalId":414778,"journal":{"name":"1997 Symposium on VLSI Technology","volume":"13 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-06-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126833059","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"A mesh-arrayed MOSFET (MA-MOS) for high-frequency analog applications","authors":"Shimomura, Matsuzawa, Kimura, Hayashi, Hirai, Kanda","doi":"10.1109/VLSIT.1997.623701","DOIUrl":"https://doi.org/10.1109/VLSIT.1997.623701","url":null,"abstract":"A 0.3 pm Mesh-mayed MaFET(MA-MOS) with ringshaped gate electrode is proposed for high-frequency analog applications. The MA-MOS achieves low noise figure (NFmin) of 0.6 dB at 2 GHz and high maximum oscillation frequency (finax) of 37 GHz, using non-salicide 0.25pm CMOS technology. The parasitic effects of MA-MOS for high frequency performance are farther discussed.","PeriodicalId":414778,"journal":{"name":"1997 Symposium on VLSI Technology","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-06-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128215295","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Dual Threshold Voltages And Substrate Bias: Keys To High Performance, Low Power, 0.1 /spl mu/m Logic Designs","authors":"Thompson, Young, Greason, Bohr","doi":"10.1109/VLSIT.1997.623699","DOIUrl":"https://doi.org/10.1109/VLSIT.1997.623699","url":null,"abstract":"We show that dual threshold voltage devices and substrate bias are needed in high performance low power O.lpm logic designs. The circuit applications of the dual threshold devices differ from previous reports. In this work, the dual threshold devices consist of a low threshold device for static CMOS circuits and a higher threshold device for noise margin sensitive dynamic circuits. Dynamic substrate bias is needed to control standby leakage resulting from the static circuits.","PeriodicalId":414778,"journal":{"name":"1997 Symposium on VLSI Technology","volume":"38 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-06-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125686008","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"An Advanced 2.5nm Oxidized Nitride Gate Dielectric For Highly Reliable 0.25/spl mu/m MOSFETs","authors":"Yamamoto, Ogura, Saito, Uwasawa, Tatsumi, Mogami","doi":"10.1109/VLSIT.1997.623687","DOIUrl":"https://doi.org/10.1109/VLSIT.1997.623687","url":null,"abstract":"Ultrathin gate dielectrics are important to realize high performance and low-voltage operation CMOS devices. An advanced ultrathin gate dielectric formation process, that is, direct nitridation of silicon and sequential oxidation, is proposed and evaluated to suppress boron penetration and to improve hot-carrier reliability. No boron penetration, longer hot-carrier lifetime and high drain current are achieved in MOSFETs with 2.5nm oxidized nitride gate dielectric.","PeriodicalId":414778,"journal":{"name":"1997 Symposium on VLSI Technology","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-06-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128975179","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"The Simplest Stacked BST Capacitor For The Future DRAMs Using A Novel Low Temperature Growth Enhanced Crystallization","authors":"Takehiro, Yamauchi, Yoshimaru, Onoda","doi":"10.1109/VLSIT.1997.623744","DOIUrl":"https://doi.org/10.1109/VLSIT.1997.623744","url":null,"abstract":"The simplest stacked capacitor with BST thinner films (about 50nm-thick) grown by a novel low temperature growth [ 11 was demonstrated. The storage node without sidewall spacer was constructed by thinner Ru-layer, sputtered-TiN diffusion barrier, TiSix electrical contact layer and poly-Si plug. The low temperature BST growth prevented the leakage current increase of BST films as thin as 25nm. Therefore, 50% step coverage BST-capacitor was performed as sidewall-less simple stacked capacitors with large storage charge.","PeriodicalId":414778,"journal":{"name":"1997 Symposium on VLSI Technology","volume":"2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-06-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133897790","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Uniformity And Reliability Of 1.5 nm Direct Tunneling Gate Oxide MOSFETs","authors":"Momose, Nakamura, Ohguro, Katsumata, Iwai","doi":"10.1109/VLSIT.1997.623672","DOIUrl":"https://doi.org/10.1109/VLSIT.1997.623672","url":null,"abstract":"INTRODUCTION Direct tunneling gate oxide MOSFETs are expected to be a good possibility not only to achieve extremely high speed digital circuit operation [l] , but also to realize RF high performance for analog applications [2]. However, there are a few concerns for the use of such ultra-thin gate oxide. One is the controllability of gate oxide film thickness in terms of gate leakage current, threshold voltage, gate breakdown, etc. Another is the reliability of the oxides in terms of time-dependent breakdown and hotcarrier injection. The third is dopant penetration from gate electrode to the substrate. This paper reports for the first time experimental results respecting the film thickness control, reliahlity, and dopant penetration of the ultra-thin gate oxide. The results suggest unexpectedly good nature of such ultra-thin gate oxide films. SAMPLE FABRICATION Figure 1 shows the fabrication process flow of ultrathin gate oxide MOSFETs. The 1.5 nm gate oxide film was produced by rapid thermal oxidation (RTO). The heat flow of the RTO is shown in Fig. 2. Figure 3 shows TEM aoss section of the ultra-thin gate oxide. N+polysilicon gate doped by phosphorus was used A low sheet resistance of 1.4 m / s q was achieved for the sourceidrain extension by solid phase diffusion of phosphorus from the PSG sidewall. The CO salicide technique was also applied to 1.5 nm gate oxide MOSFETs. The resulting sheet resistance of the silicide layers is about 4 Wsq. RESULTS AND DISCUSSIONS Figure 4shows the distributions of gateleakage current (a), gate breakdown voltage (b), and threshold voltage (c) in a 6-inch wafer. The definition of the leakage current and breakdown voltage is shown in Fig. 4-(d). Despite no special care being taken to control film thickness at RTO, excellent uniformity in the distributions was confirmed. In fact, sigmas of the leakage current, breakdown voltage and Vth are 6.9, 2.5 and 1.7 %, respectively. The leakage current is very sensitive to the oxide thickness and the sigma value of 6.9 % in the leakage current of the capacitor corresponds to the oxide film thickness variation within only 0.025 nm at 3 sigma, as shown in Fig. 4-(a). This value is much better than expected. h e to the excellent gate thickness uniformity, the variations of the breakdown voltage and threshold voltage are very smal l in a wder. It should be noted that there is no A or B mode failure for the breakdown and that the threshold voltages of all the transistors are within normal range. Figure 5 shows TEM observation of the oxide film during an early stage of the RTO. Even at the veq bepnning of the oxidation at 2 seconds, good uniformity of the film was observed. Figure 6 shows the TDDB characteristics of the ultrathin gate oxide hlOSFETs in comparison with thicker gate oxide MOSFETs at 3.0 and 5.0 nm. Constant stress voltage was applied for 100 seconds and the voltage was increased with step by step as shown in Fig. 6-(a). Oxide breakdown was judged to occur when the ","PeriodicalId":414778,"journal":{"name":"1997 Symposium on VLSI Technology","volume":"52 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-06-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127054242","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"A 0.18/spl mu/m CMOS Process Using Nitrogen Profile-engineered Gate Dielectrics","authors":"Grider, Nicollian, Kuehne, Brown, Aur, Eklund, Pas, Hunter, Douglas","doi":"10.1109/VLSIT.1997.623688","DOIUrl":"https://doi.org/10.1109/VLSIT.1997.623688","url":null,"abstract":"A novel gate dielectric, with nitrogen confined within the top 0.7nm of the oxide surface, has been demonstrated in a 0.18pm CMOS process. High nitrogen concentrations (>lo%), incorporated by remote plasma nitridation (RPN), are demonstrated to suppress boron penetration in 4.0nm gate dielectrics with no degradation in n-ch or p-ch mobility. Drive currents with the RPN oxide were equivalent to, or exceeded those obtained with an Si02 control. Various gate doping schemes were explored to quantify contributions of poly depletion and Rsd on device performance. It was found that poly depletion accounts for less than one-half of the drive current improvement when PMOS source/drain doping is increased.","PeriodicalId":414778,"journal":{"name":"1997 Symposium on VLSI Technology","volume":"63 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-06-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123241001","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"A Novel Flash Memory Device With S Plit Gate Source Side Injection And 0N0 Charge Storage Stack (SPIN)","authors":"Wei-ming Chen, Swift, Roberts, Forbes, Higman, Maiti, Paulson, Kuo-tung Chang","doi":"10.1109/VLSIT.1997.623696","DOIUrl":"https://doi.org/10.1109/VLSIT.1997.623696","url":null,"abstract":"This paper discusses a novel flash memory featuring a selfaligned split gate structure with sub-0.lpm sidewall gate length, source side injection for programming, band-to-band tunneling for erasing, and an oxide/nitride/oxide (ONO) stack for charge storage. The bitcell is suitable for low voltage (1.8V) and high density (cell size 1.35 km2 using 0.4 Fm technology) applications.","PeriodicalId":414778,"journal":{"name":"1997 Symposium on VLSI Technology","volume":"240 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-06-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131503654","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Technology And Power-speed Trade-offs In Quantum-dot And Nano-crystal Memory Devices","authors":"Tiwari, Welser, Rana","doi":"10.1109/VLSIT.1997.623734","DOIUrl":"https://doi.org/10.1109/VLSIT.1997.623734","url":null,"abstract":"Introduction provides better immunity, if the interface state density is low Ouantum-dot and nano-cvstal Flash memories [1-5] are sinand the nano-crystal size distribution is narrow. &-element memory devices that utilize dimensional scaling of the floating gate to achieve observable room temperature threshold voltage shifts with charge storage on the order of only a few electrons. With no storage capacitor needed, these devices are attractive for both volatile and non-volatile applications due to their small size and easy integration with logic transistors. However, the path to the judicious application of nanometer size structures and electron Confinement in solving the problems of mainstream technology remains unclear. Here we demonstrate the necessary design trade-offs in oxide, channel, and storage-dot dimensions with respect to write and erase speeds, retention time, and power, by using measured room temperature characteristics and self-consistent calculations to study the technology-performance concerns for the practical use of these memories.","PeriodicalId":414778,"journal":{"name":"1997 Symposium on VLSI Technology","volume":"185 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-06-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132584487","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}