Technology And Power-speed Trade-offs In Quantum-dot And Nano-crystal Memory Devices

Abstract

Introduction provides better immunity, if the interface state density is low Ouantum-dot and nano-cvstal Flash memories [1-5] are sinand the nano-crystal size distribution is narrow. &-element memory devices that utilize dimensional scaling of the floating gate to achieve observable room temperature threshold voltage shifts with charge storage on the order of only a few electrons. With no storage capacitor needed, these devices are attractive for both volatile and non-volatile applications due to their small size and easy integration with logic transistors. However, the path to the judicious application of nanometer size structures and electron Confinement in solving the problems of mainstream technology remains unclear. Here we demonstrate the necessary design trade-offs in oxide, channel, and storage-dot dimensions with respect to write and erase speeds, retention time, and power, by using measured room temperature characteristics and self-consistent calculations to study the technology-performance concerns for the practical use of these memories.