1997 Symposium on VLSI Technology最新文献

{"title":"Salicides for 0.10 /spl mu/m gate lengths: a comparative study of one-step RTP Ti with Mo doping, Ti with pre-amorphization and Co process","authors":"Kittl, Qi-Zhong Hong, Chih-Ping Chao, Ih-Chin Chen, Ning Yu, O'Brien, Hanratty","doi":"10.1109/VLSIT.1997.623716","DOIUrl":"https://doi.org/10.1109/VLSIT.1997.623716","url":null,"abstract":"A study of 0.10 pm gate sheet resistance and the most relevant device characteristics comparing Ti salicide with preamorphization, Ti salicide with Molybdenum doping, and CO salicide in a fully integrated 0.18~ 1.5V CMOS technology is presented for the first time. We report the first one-step RTP Ti salicide process with MO achieving low (mean=7, max=8.1 R/sq) sheet resistance at 0.10 pn gate lengths, which results in a 34% increase in n- and PMOS DRIVE by eliminating the silicide anneal step. While low 0. lop gate sheet resistances are achieved with all these processes (a) TiSiz with MO doping of gate only and (b) COS& with high temperature RTP appear as the best suited salicides for scaled technologies with low DIODE and high DRIVE In contrast (a) DIODE increases when source and drains are also doped with MO and (b) R~D increases with As or Ge preamorphization notably as junctions are scaled down.","PeriodicalId":414778,"journal":{"name":"1997 Symposium on VLSI Technology","volume":"72 6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-06-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124863250","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Advanced Gate-stack Architecture For Low-voltage Dual-workfunction CMOS Technologies With Shallow Trench Isolation","authors":"Schwalke, Kerber, Koller, Ludwig, Seidl","doi":"10.1109/VLSIT.1997.623700","DOIUrl":"https://doi.org/10.1109/VLSIT.1997.623700","url":null,"abstract":"In this work we present the advanced gate-stack architecture EXTIGATE (Extended Trench Isolation GAte TEchnology) which solves major problems associated with n+/p+ dual workfunction gate technology and shallow-trench-isolation (STI). These achievements are realized without an increase in process complexity. Furthermore, the process window is enlarged leading to a robust low-voltage dual-workfunction STI-CMOS process.","PeriodicalId":414778,"journal":{"name":"1997 Symposium on VLSI Technology","volume":"255 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-06-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122361464","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"The 300mm Technology Current Status And Future Prospect","authors":"Komiya","doi":"10.1109/VLSIT.1997.623667","DOIUrl":"https://doi.org/10.1109/VLSIT.1997.623667","url":null,"abstract":"Development of the 300¿ technology is approaching the exciting part of the program. The transition in the wafer diameter fiom 200¿ to 300¿ is expected to result in the chip cost reduction by the range of 1.520% and to decrease the investment in the production line down to about 65%. The technological key issues would be the crystal growth and the heat treatment. World-wide cooperative efforts are being made for the evaluation of the equipment and materials and for the standardiition.","PeriodicalId":414778,"journal":{"name":"1997 Symposium on VLSI Technology","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-06-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129323384","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Fully Planarized Stacked Capacitor Cell With Deep And High Aspect Ratio Contact Hole For Gigs-bit DRAM","authors":"Itabashi, Tsuboi, Nakamura, Hashimoto, Futoh, Fukuda, Hanyu, Asai, Kawamura, Yao, Takagi, Ohta, Karasawa, Iio, Inoue, Nomura, Satoh, Higashimoto, Matsumiya, Miyabo, Ikeda, Yamazaki, Miyajima, Watanabe, Taguchi","doi":"10.1109/VLSIT.1997.623675","DOIUrl":"https://doi.org/10.1109/VLSIT.1997.623675","url":null,"abstract":"A fully planarized stacked capacitor cell for lGiga bit DRAM and beyond having three significant features has been developed. First, all the lithograpluc processes were performed on the planarized surface to achieve enough margin. Second, the patterns in critical layers were arranged to be suitable for alternating Phase Shift Mask(PSM). Third, deep contact hole resulting from introducing global planarization was adopted in a reasonable size. The cell area of 0.26um2 (0.36 x 0.72~) can be fabricated with a KrF excimer stepper using five alternating PSMs and two half tone PSMs. 1 nt rod ucti o n DRAM process development has been hghly depend on the development of lithographic technologies. But optical lithography is now facing severe problems such as wavelength limitation and insufficient overlay accuracy. Moreover, the steps between cell array and peripheral circuit area become serious problem more and more to perform DRAM process because the cell capacitance has to be maintained in each generation. The steps require a large depth of focus (DOF), restrict a design rule scaling, and also make etching of first metal layer very difficult. As a result, the chip size will be larger. To overcome the above problems, we have selected photo-lithography-fiiendly technology which means straight line and space pattern, fully planarized surface, and adopting alternating PSM. We also used a self aligned contact (SAC) technology to achieve 8F2 cell size. The fully planarized cells were reported, but they used larger cell size and relaxed design A global planarization is very attractive, but has disadvantage, which is deep and hence high aspect ratio (HAR) contact hole. We have fabricated and confumed contact resistance and junction leakage with HAR contact hole necessitated by global planarization after capacitor formation in 0.1 Sum rule. This paper describes a novel DRAM cell concept and fabrication process in 0.18~ rule with HAR contact for the fxst time.","PeriodicalId":414778,"journal":{"name":"1997 Symposium on VLSI Technology","volume":"284 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-06-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114373997","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Boron Implanted Shallow Junction Formation By High-temperature/ Short-time/high-ramping-rate(400/spl deg/C/sec) RTA","authors":"Shishiguchi, Mineji, Hayashi, Saito","doi":"10.1109/VLSIT.1997.623709","DOIUrl":"https://doi.org/10.1109/VLSIT.1997.623709","url":null,"abstract":"This paper proposes a novel 50nm-depth shallow junction formation for realizing low SD-extension resistance in deep sub-quarter micron PMOS-FETs. In this technology, the extension is fabricated by Ge'(5keV) pre-amorphizised lowenergy B'( 1 keV) implantation, followed by optimized RTA condition (1 100°C for 50msec with ramping-rate 400\"C/sec). It has become apparent that this optimized condition yields the lower resistance-limit(300~/sq) for 50nm-depth junction, when using ion implantation process. S/D series resistance for the O.15ym-PMOS(W= IOym) fabricated by this technology is reduced to 140R. This result shows that high-performance deep sub-quarter micron CMOS-FETs are realized by the optimization of ion implantation and/or RTA process.","PeriodicalId":414778,"journal":{"name":"1997 Symposium on VLSI Technology","volume":"84 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-06-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134341331","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"A Novel 1b Trench DRAM Cell With Raised Shallow Trench Isolation (RSTI)","authors":"Alsmeier, Kelleher, Beintner, Haensch, Mandelman, Hoh, Ninomiya, Srinivasan, Bronner","doi":"10.1109/VLSIT.1997.623674","DOIUrl":"https://doi.org/10.1109/VLSIT.1997.623674","url":null,"abstract":"The progressive scaling of Dd cells towards 8F2 for the 1G generation and beyond requires to design, both channel length and width of the array device in minimum dimensions. Historically the DRAM array device was kept conservatively large to ensure a wide process window for the stringent off current requirement as well as a relaxed doping level to minimize junction fields and leakage [l]. In thls paper , data is presented showing that narrow width effects become dominant in the array transistor design and control of the comer device associated with the shallow trench isolation becomes crucial. A novel Raised Shallow Trench Isolation (RSTI) is proposed as a way of structurally reducing the influences of STI related comer conduction on threshold voltage. This scheme was introduced earlier for the purpose of reducing the size of NAND EEPROM [2] and SRAM cells [3] as well as for a CMOS process [4] . We show its integration into a DRAM cell for the first time and present data showing the extremely tight control of array threshold voltage achievable with this process.","PeriodicalId":414778,"journal":{"name":"1997 Symposium on VLSI Technology","volume":"46 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-06-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131406160","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Physical Model For Contact Degradation At High Current Densities","authors":"Neugroschel, Chih-Tang Sah","doi":"10.1109/VLSIT.1997.623685","DOIUrl":"https://doi.org/10.1109/VLSIT.1997.623685","url":null,"abstract":"A new physical model on electrical degradation of the metaYpolysilicodsilicon contact at high current densities is presented and verified by experiments. Results from submicron n+poly/n+emitter/p-base/n+collector bipolar transistors indicate that the observed contact instabilities are reaction rate limited by transient dehydrogenation and hydrogenation at the n+poly/n+emitter interface and steady-state dehydrogenation at the metal/n+poly interface. Introduction Scaling down transistors in present and future integrated circuits increases the current densities which pass through the interconnect/silicon contacts. Thus, the long-term stability of the contacts in BJTs and MOSTs can be a potential reliability problem. Instabilities of the emitter contact resistance RE and current gain pF were observed in submicron B JT’s with metal/n+poly-silicon/n+siliconemitter (metaVn+poly/n+emitter) structure when stressed at h i g h f o r w a r d e m i t t e r c u r r e n t d e n s i t y JE-s t ress > -1.0mA/pm2 [ 1-31. Detail experiments on contact instability were reported recently [3] showing increasing and decreasing pF with stress time and two rate constants both with A,J, + A,Ji dependency. These dependencies were attributed to the hydrogenation and dehydrogenation reactions at the metal/poly-Si and poly-Si/c-Si interfaces. However, a viable physics-based theory to explain and model the instability dependencies on current density was not given in [3] which is presented here. Model and Experiments Figure 1 (a) shows the hydrogenation-dehydrogenation pathways in the metal/n+poly/n+emitter structure of the BJT used in the experiment and the physical model development [4]. Electrons (filled circles) flow into the contact which is forward-biased to V, = 1V to 2V. Holes (open circles) are injected from the p-base into the n+poly and n+emitter layers. The limiting transient reaction is the hydrogenation-dehydrogenation at the n+poly/n+emitter interface which decrease-increase respectively the density of the interfacial silicon and oxygen dangling bonds, Si. and SiO., where electrons and holes recombine to give I, and control pF. The rate equation for the density of one interfacial trap species, nIT(t), its solution for a steady-state hydrogen concentration, and the rate constants are given below which account for all the experimental variations observed in [31. Metal n+polySi ncEmitter p-Base Fig.1 Creation and destruction of interface traps i n the metal/n+poly/n+emitter/p-base contact layers at high forward current densities. (a) Cross-section with kinetics pathways. (b) Transition energy band diagram. NITT in (3) i s t h e t o t a l i n t e r f a c i a l t r a p d e n s i t y , hydrogenated plus not-hydrogenated. The initial and final value, nIT(t=O)=NIT0 and nIT(t=m)ENITm determines whether pF decreases (NIT0 < NIT,) or increases (NIT? > NIT,) with s t r e s s t i m e , wh ich i s c o n s i s t e n t wi th 41 4-93081 3-75-1 197 1997 Symposium on VLSl Technolog","PeriodicalId":414778,"journal":{"name":"1997 Symposium on VLSI Technology","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-06-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128521938","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Implication And Solutions For Joule Heating In High Performance Interconnects Incorporating Low-k Dielectrics","authors":"Shih, Chang, Havemann, Levine","doi":"10.1109/VLSIT.1997.623706","DOIUrl":"https://doi.org/10.1109/VLSIT.1997.623706","url":null,"abstract":"","PeriodicalId":414778,"journal":{"name":"1997 Symposium on VLSI Technology","volume":"220 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-06-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129674598","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"A Novel Environmentally-friendly Corrosion-free Post-stripping Rinsing Procedure After Solvent Strip","authors":"Vos, Rotondaro, Mertens, Meuris, Heyns","doi":"10.1109/VLSIT.1997.623683","DOIUrl":"https://doi.org/10.1109/VLSIT.1997.623683","url":null,"abstract":"Corrosion of metal lines during the post-stripping rinse is a severe problem in multi-level metallization processes. In this paper it is demonstrated that the addition of small amounts of the inorganic acid HNO3 to the ultrapure water used for rinsing can effectively be used to suppress this corrosion without the need of an additional IPA- step.","PeriodicalId":414778,"journal":{"name":"1997 Symposium on VLSI Technology","volume":"66 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-06-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127110085","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Fast Parallel Programming Of Multi-level NAND Flash Memory Cells Using The Booster-line Technology","authors":"Choi, Kim, Shin, Mang, Ahn","doi":"10.1109/VLSIT.1997.623697","DOIUrl":"https://doi.org/10.1109/VLSIT.1997.623697","url":null,"abstract":"Introduction With this programming method, a program speed of 300 ,us, which is equivalent to that of the single bit NAND cell, is The Multi-Level Cell (MLC) technology is essential in achieved. The parallel programming with booster-lines significantly reducing the bit cost of flash memories [I]. results in a significant improvement over the conventional The MLC, however, has drawbacks such as high MLC which requires a high programming voltage of over 20 programming voltage, longer programming time and V and prolonged programming time [ 11. increased disturbances. We demonstrated in the Dast that the booster plate Multi-Level Cell Characteristics NAND flash technology enhances the program speed and eliminates the program disturbance [2]. In this paper, we report a new fast parallel programming method for MLC NAND. With the addition of booster-lines to the cell strings, the program speed of each NAND string can be controlled by the booster-line bias. This method in essence is to obtain different cell threshold voltages ( v t h ) at a given programming time by controlling the program voltage of individual memory cells. Thus the four-level MLC with programming speed and reliability comparable to those of the single bit NAND cell is achieved. Fig. 4 shows that the measured Vth’s of the four-level cell array (4k bits) have tight distributions of less than 0.5 V. The erase characteristics are almost independent of the Vth levels as shown in Fig. 5 . Due to high programming voltage and long programming time, unselected cells in conventional MLC’s are exposed to increased disturbances. The adoption of booster-lines, however, results in a wide Vpws zone without Program voltage disturbance (Vpgm stress) and Vpass stress at pass voltage less than 7 V, as shown in Fig. 6. The complete disappearence of the Vpgm stress is caused by the enhanced self-boosting action in program inhibited cells by boosterlines [2]. It is important to have enough sensing margin in MLC because of the reduced Vth windows. The “ON” cell string current is the smallest when the difference between the cell Cell Structure and Operation","PeriodicalId":414778,"journal":{"name":"1997 Symposium on VLSI Technology","volume":"123 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-06-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130006227","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}