A Novel 1b Trench DRAM Cell With Raised Shallow Trench Isolation (RSTI)

Abstract

The progressive scaling of Dd cells towards 8F2 for the 1G generation and beyond requires to design, both channel length and width of the array device in minimum dimensions. Historically the DRAM array device was kept conservatively large to ensure a wide process window for the stringent off current requirement as well as a relaxed doping level to minimize junction fields and leakage [l]. In thls paper , data is presented showing that narrow width effects become dominant in the array transistor design and control of the comer device associated with the shallow trench isolation becomes crucial. A novel Raised Shallow Trench Isolation (RSTI) is proposed as a way of structurally reducing the influences of STI related comer conduction on threshold voltage. This scheme was introduced earlier for the purpose of reducing the size of NAND EEPROM [2] and SRAM cells [3] as well as for a CMOS process [4] . We show its integration into a DRAM cell for the first time and present data showing the extremely tight control of array threshold voltage achievable with this process.