{"title":"Fully Planarized Stacked Capacitor Cell With Deep And High Aspect Ratio Contact Hole For Gigs-bit DRAM","authors":"Itabashi, Tsuboi, Nakamura, Hashimoto, Futoh, Fukuda, Hanyu, Asai, Kawamura, Yao, Takagi, Ohta, Karasawa, Iio, Inoue, Nomura, Satoh, Higashimoto, Matsumiya, Miyabo, Ikeda, Yamazaki, Miyajima, Watanabe, Taguchi","doi":"10.1109/VLSIT.1997.623675","DOIUrl":null,"url":null,"abstract":"A fully planarized stacked capacitor cell for lGiga bit DRAM and beyond having three significant features has been developed. First, all the lithograpluc processes were performed on the planarized surface to achieve enough margin. Second, the patterns in critical layers were arranged to be suitable for alternating Phase Shift Mask(PSM). Third, deep contact hole resulting from introducing global planarization was adopted in a reasonable size. The cell area of 0.26um2 (0.36 x 0.72~) can be fabricated with a KrF excimer stepper using five alternating PSMs and two half tone PSMs. 1 nt rod ucti o n DRAM process development has been hghly depend on the development of lithographic technologies. But optical lithography is now facing severe problems such as wavelength limitation and insufficient overlay accuracy. Moreover, the steps between cell array and peripheral circuit area become serious problem more and more to perform DRAM process because the cell capacitance has to be maintained in each generation. The steps require a large depth of focus (DOF), restrict a design rule scaling, and also make etching of first metal layer very difficult. As a result, the chip size will be larger. To overcome the above problems, we have selected photo-lithography-fiiendly technology which means straight line and space pattern, fully planarized surface, and adopting alternating PSM. We also used a self aligned contact (SAC) technology to achieve 8F2 cell size. The fully planarized cells were reported, but they used larger cell size and relaxed design A global planarization is very attractive, but has disadvantage, which is deep and hence high aspect ratio (HAR) contact hole. We have fabricated and confumed contact resistance and junction leakage with HAR contact hole necessitated by global planarization after capacitor formation in 0.1 Sum rule. This paper describes a novel DRAM cell concept and fabrication process in 0.18~ rule with HAR contact for the fxst time.","PeriodicalId":414778,"journal":{"name":"1997 Symposium on VLSI Technology","volume":"284 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1997-06-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"9","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"1997 Symposium on VLSI Technology","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/VLSIT.1997.623675","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 9
Abstract
A fully planarized stacked capacitor cell for lGiga bit DRAM and beyond having three significant features has been developed. First, all the lithograpluc processes were performed on the planarized surface to achieve enough margin. Second, the patterns in critical layers were arranged to be suitable for alternating Phase Shift Mask(PSM). Third, deep contact hole resulting from introducing global planarization was adopted in a reasonable size. The cell area of 0.26um2 (0.36 x 0.72~) can be fabricated with a KrF excimer stepper using five alternating PSMs and two half tone PSMs. 1 nt rod ucti o n DRAM process development has been hghly depend on the development of lithographic technologies. But optical lithography is now facing severe problems such as wavelength limitation and insufficient overlay accuracy. Moreover, the steps between cell array and peripheral circuit area become serious problem more and more to perform DRAM process because the cell capacitance has to be maintained in each generation. The steps require a large depth of focus (DOF), restrict a design rule scaling, and also make etching of first metal layer very difficult. As a result, the chip size will be larger. To overcome the above problems, we have selected photo-lithography-fiiendly technology which means straight line and space pattern, fully planarized surface, and adopting alternating PSM. We also used a self aligned contact (SAC) technology to achieve 8F2 cell size. The fully planarized cells were reported, but they used larger cell size and relaxed design A global planarization is very attractive, but has disadvantage, which is deep and hence high aspect ratio (HAR) contact hole. We have fabricated and confumed contact resistance and junction leakage with HAR contact hole necessitated by global planarization after capacitor formation in 0.1 Sum rule. This paper describes a novel DRAM cell concept and fabrication process in 0.18~ rule with HAR contact for the fxst time.
开发了一种用于lGiga位及以上DRAM的完全平面化堆叠电容器电池,具有三个重要特征。首先,所有的光刻过程都在平面表面进行,以获得足够的余量。其次,对关键层的图形进行了适合于交变相移掩模(PSM)的排列。三是采用合理尺寸的引入全局平面化后形成的深接触孔。使用5个交变psm和2个半音psm,可以用KrF准分子步进制得0.26um2 (0.36 x 0.72~)的细胞面积。DRAM工艺的发展在很大程度上依赖于光刻技术的发展。但光刻技术目前面临着波长限制和覆盖精度不足等严重问题。此外,由于每一代都要保持单元电容,因此单元阵列与外围电路区域之间的间距问题越来越严重。这些步骤需要很大的焦深(DOF),限制了设计规则的缩放,也使得第一金属层的蚀刻非常困难。因此,芯片尺寸将更大。为了克服上述问题,我们选择了光刻友好技术,即直线和空间图案,完全平面化的表面,采用交替的PSM。我们还使用了自对准接触(SAC)技术来实现8F2单元尺寸。完全平面化的细胞有报道,但它们使用了更大的细胞尺寸和宽松的设计。整体平面化是非常有吸引力的,但缺点是接触孔深,因此高纵横比(HAR)。在0.1 Sum规则下,我们制作并混淆了电容形成后全局平面化所需要的HAR接触孔的接触电阻和结漏。本文首次提出了一种新的具有HAR接触的0.18~规则的DRAM单元概念和制造工艺。