1997 Symposium on VLSI Technology最新文献_第2页

Modeling And Characterization Of N/sup +/- And P/sup +/-polysilicon-gated Ultra Thin Oxides (21-26 /spl Aring/) N/sup +/-和P/sup +/-多晶硅门控超薄氧化物(21-26 /spl Aring/)的建模与表征

1997 Symposium on VLSI Technology Pub Date : 1997-06-10 DOI: 10.1109/VLSIT.1997.623742

Lo, Buchanan, Taur, Han, Wu

引用次数: 41

A Highly Reliable 0.35/spl mu/m Field-shield Body-tied SOI Gate Array For Substrate-bias-effect Free Operation 用于无衬底偏置效应工作的高可靠0.35/spl mu/m场屏蔽体系SOI门阵列

1997 Symposium on VLSI Technology Pub Date : 1997-06-10 DOI: 10.1109/VLSIT.1997.623711

Maeda, Yamaguchi, Kim, Iwamatsu, Ipposhi, Miyamoto, Hirano, Ueda, Nii, Mashiko, Maegawa, Inoue, Nishimura

引用次数: 4

Transient-enhanced Diffusion Of Iridium And Its Eflects On Electrical Characteristics Of Deep Sub-micron nMOSFETs 铱的瞬态增强扩散及其对深亚微米nmosfet电特性的影响

1997 Symposium on VLSI Technology Pub Date : 1997-06-10 DOI: 10.1109/VLSIT.1997.623707

Cao, Griffin, Vande Voorde, Diaz, Greene

{"title":"Transient-enhanced Diffusion Of Iridium And Its Eflects On Electrical Characteristics Of Deep Sub-micron nMOSFETs","authors":"Cao, Griffin, Vande Voorde, Diaz, Greene","doi":"10.1109/VLSIT.1997.623707","DOIUrl":"https://doi.org/10.1109/VLSIT.1997.623707","url":null,"abstract":"ABSTRACT RESULTS and DISCUSSION Accurate 2D doping profiles are needed to simulate shortFig. 2 shows measured C-V curves and simulations fits for channel nMOSFETs with indium channel. BY combining a lOOpm x 100pm nMOSFET. Excellent fit was established indium transient-enhanced diffusion (TED), segregation, and thoughout the C v curves for the 1D case. The kink near quantum mechanical (OM) effects, c V curves measured on the flat-band part of the C-V curve is due to the high nMOSFETs with various gate lengths can be simulated ionization energy (0.16 eV) of indium [5], and is confirmed accurately. Although indium exhibits severe TED, the by measuring C-V curves at various temperatures (Fig. 3). reverse-short-channel effect (RSCE) is reduced due to the for an indium-doped 0.2 strong segregation of indium into the gate oxide. In addition, gate n ~ ~ ~ ~ ~ ~ . B~ combining the effect of TED diffusion experiments using a buried indium marker layer on indium with the experimentally observed strong confirms that indium has severe TED, similar to boron, segregation into the gate oxide [6 ] , the 2D indium profile can which can be reduced by using an RTA after an implant. be accurately captured and the fit of the C-V curves is excellent. Fig. 5 shows the change in doping contours with candidate for achieving a retrograde and without considering indium TED and segregation effects. profile (RCP) in deep sub-micron ~ O S F E T ~ [I] , TED pushes indium towards the surface because of point H ~ ~ ~ ~ ~ ~ , transient-edanced difhsion (TED) due to ion defect gradients and reduces the peak indium concentration. implantation damage can excessive dopant diffusion In addition, the TED of indium allows indium to reach the which severely affects MOSFET~ characteristics [21, Until heavily doped source/drain regions by electric field assisted now, little has been reported on how the TED of indium dif is ion where indium is trapped in the highly doped n-type affects redistribution of the channel dopant profile. In this region. Due to the strong segregation of indium into the gate work, a C-V technique was used to obtain detailed 213 indium oxide, the amount of indium pileup near the surface is channel profiles, and a TED model for indium was extracted reduced, and consequently, the RSCE in an indium channel [3]. Diffusion experiments based on buried indium marker device is smaller compared to a boron channel device as layer were used to monitor the TED of indium due to ion shown in Fig. 6. implantation damage. ~ i ~ . 4 shows the C-V","PeriodicalId":414778,"journal":{"name":"1997 Symposium on VLSI Technology","volume":"20 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-06-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127822165","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 9

Charging And Intrinsic-leakage Current Peaks In Thin Silicon-dioxide Films 二氧化硅薄膜中的充电和本征泄漏电流峰值

1997 Symposium on VLSI Technology Pub Date : 1997-06-10 DOI: 10.1109/VLSIT.1997.623741

Yamada, Yugami, Ohkura

引用次数: 7

New Insight On Electromigration Failure Mechanism And Its Impact On Design Guidelines 电迁移失效机制的新认识及其对设计准则的影响

1997 Symposium on VLSI Technology Pub Date : 1997-06-10 DOI: 10.1109/VLSIT.1997.623684

Jawarani, Gall, Hernández, Capasso, Kawasaki

引用次数: 2

Gate Electrode Engineering By Control Of Grain Growth For High Performance And High Reliable 0.18/spl mu/m Dual Gate CMOS 高性能高可靠0.18/spl mu/m双栅CMOS的晶粒生长控制栅电极工程

1997 Symposium on VLSI Technology Pub Date : 1997-06-10 DOI: 10.1109/VLSIT.1997.623718

Shimizu, Kuroi, Sayama, Furukawa, Nishida, Inoue, Inuishi, Nishimura

引用次数: 8

Ultra-thin Ta/sub 2/O/sub 5/SiO/sub 2/ gate insulator with TiN gate technology for 0.1/spl mu/m MOSFETs 超薄Ta/sub 2/O/sub 5/SiO/sub 2/栅极绝缘子，采用TiN栅极技术，用于0.1/spl mu/m mosfet

1997 Symposium on VLSI Technology Pub Date : 1997-06-10 DOI: 10.1109/VLSIT.1997.623735

Momiyama, Minakata, Sugii

{"title":"Ultra-thin Ta/sub 2/O/sub 5/SiO/sub 2/ gate insulator with TiN gate technology for 0.1/spl mu/m MOSFETs","authors":"Momiyama, Minakata, Sugii","doi":"10.1109/VLSIT.1997.623735","DOIUrl":"https://doi.org/10.1109/VLSIT.1997.623735","url":null,"abstract":"We have developed a new Ta205/Si02 gate insulator with a TIN gate electrode technology to break through the limitation of a thin SiOz gate insulator with a poly-Si electrode. We successfully fabricated nMOSFETs with stable operation and high drive current for the first time. Ultra thin chemically oxidized SiOz (less than 2 nm) combined with Ta205 provides a stable interface which improves Gm and reliability of transistor. High drive current (Idmax = 0.74 mA/pm at Vg = Vd = 3.0V) and good sub-threshold slope (S-factor = 76 mV/dec.) were obtained with Teq of 2.8nm and gate length of 0.35 Hm nMOSFETs. Introduction Deep sub-micron devices of less than 0.1 pm encounter a scaling limit of the Si02 gate insulator because of its high leakage current due to direct tunneling effects. The gate depletion effect is also serious issue for such devices. In order to break through these problems, we have to develop a new high Er gate insulator material having thick physical thickness and metal-gate technology. TazO5 (Er = 25 in bulk) and TiN are most promising candidates for future gate insulator and gate electrode materials respectively'). Though intensive investigations about Ta205 have been done for storage capacitors in future G-bit scale DRAMsZ4), there are no reports on Ta205 used for gate insulator for deep sub-micron devices. In view of mobility and reliability, we have developed Ta205/Si02 system for gate insulator with an equivalent Si02 thickness of less than 5 nm and TIN gate technology, and fabricated 0.35 pm nMOSFETs. One concern with the use of Si02 as an interlayer is its thickness and controllability. Since an insulator film thickness of less than 3 nm is required for 0.1 pm transistors, the SiOz interlayer should be very thin (less than 2 nm) so as not to suppress the advantage of utilizing high Er material. We have grown an ultra thin S O z interlayer by HNO, boiling and Nz annealing at temperatures of 700°C or 800°C for 30 min. Fabrication Process Figure 1 shows a process flow and schematic cross section of a Taz05/Si02 gate insulator nMOSFET. Following the conventional LOCOS isolation, the Si active region was oxidized by various methods as listed in Table 1 . Si02 thicknesses are calculated from Si 2p X P S spectra. We also prepared the non-oxidation sample by dipping HF solution before the TazO5 CVD as a control. TazO5 films were deposited by LPCVD at 410°C using Ta(OC2H5)5 and O2 gases. These films were annealed in O2 ambient at 800°C for 60 sec TIN was sputtered on Ta205 films as the gate electrode. After the gate definition, the source and drain were formed by ion implantation of As' to fabricate single-drain nMOSFETs. Impurity activation was done by RTA at 800°C for 60 sec. Other process and device parameters are also listed in Table 1. Teq are calculated from capacitance data under the accumulation condition using large MOS diodes Results and Discussion Figure 2 and Figure 3 show typical I-V and sub-threshold characteristics for a samp","PeriodicalId":414778,"journal":{"name":"1997 Symposium on VLSI Technology","volume":"66 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-06-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126030458","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 20

A Simple Sub-0.3/spl mu/m CMOS Technology With Five-level Interconnect Using Al-plug And HSQ Of Low-k For High Performance Processor 一种用于高性能处理器的简单的0.3/spl μ m以下5级互连al插头和低k HSQ的CMOS技术

1997 Symposium on VLSI Technology Pub Date : 1997-06-10 DOI: 10.1109/VLSIT.1997.623692

Yoshiyama, Okada, Igarashi, Yamada, Shimizu, Takata, Osaki, Higashitani, Asai

{"title":"A Simple Sub-0.3/spl mu/m CMOS Technology With Five-level Interconnect Using Al-plug And HSQ Of Low-k For High Performance Processor","authors":"Yoshiyama, Okada, Igarashi, Yamada, Shimizu, Takata, Osaki, Higashitani, Asai","doi":"10.1109/VLSIT.1997.623692","DOIUrl":"https://doi.org/10.1109/VLSIT.1997.623692","url":null,"abstract":"A simple sub-0.3ym CMOS technology has been developed with high performance transistors and five level interconnects. Using aluminum plug and HSQ (Hydrogen Silsesquioxane) film of low-k, the total process time is reduced by about 20% as compared with the conventional process with tungsten plug. The multimedia processor of 250MHz operation has been built on this technology. INTRODUCTION It is well known that faster transistors and multi-level interconnects will be required to maintain historic density and performance trends for high performance processor. Process steps of interconnects for total process steps are increase as generation of process technology is run. In generally, a tungsten plug(W-plug) for hole filling and AlCu materials for interconnect layer are used. Wplug is formed by blanket tungsten deposition followed by chemical mechanical polishing or etch back. This paper describes a simple logic process that meets the density and performance. This process is based on three key technologies such as faster transistor with CO salicide, aluminum plug (Al-plug), HSQ film of low-k. RESULTS AND DISCUSSION Interconnect Figure 1 shows the cross sectional view of this CMOS structure with five level interconnect. The pitches and sheet resistances of the interconnect layers are summarized in table 1. M1, M2 and M3 use a fine pitch to optimize density and capacitance for short distance interconnect. M4 and M5 use a course with thick metal to reduce parasitic resistance for long distance interconnect. In order to achieve low via resistance, good electromigration and reduction of the process time, Al-plug using high pressure[ 1][2] is adopted instead of W-plug for contact and via hole.Figure 2 shows the resistance of 3000 via chains for Al-plug and W-plug, respectively. Hole size is 0.35 x 0.35 ym2. The resistance of Al-plug is smaller by 45% than that of W-plug. Figure 3 shows comparison of the process time between Wplug and Al-plug. The process time reduction of 30% for interconnect process and 20% reduction for total process can be achieved in this Al-plug interconnect compared to the conventional W-plug interconnect. Because, aluminum PVD process using high pressure can form plug and wire at the same time. Figure 4 shows interconnect capacitances as a function of the device feature size. As the dimension shrink, the ratio of coupling capacitance to the total interconnect capacitance is increase. In this work, HSQ with low dielectric constant (k=3.6) was adopted to reduce the coupling capacitance.The inter-level dielectric was formed as follows; After the metal layer patterning, thin plasma TEOS was deposited by plasma CVD method. HSQ was applied as a spin-on layer on the plasma TEOS film. It is easy to fill gaps because HSQ has low viscosity resistance. After deposition of thick plasma TEOS, the TEOS film was planarized by CMP. Then, thin plasma TEOS was deposited to adjust the dielectric thickness. Via holes were pattemed using attenuated phase s","PeriodicalId":414778,"journal":{"name":"1997 Symposium on VLSI Technology","volume":"45 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-06-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133641148","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 1

Modeling And Characterization Of Si/SiO/sub 2/ Interface Roughness Si/SiO/ sub2 /界面粗糙度建模与表征

1997 Symposium on VLSI Technology Pub Date : 1997-06-10 DOI: 10.1109/VLSIT.1997.623686

Heng-Chih Lin, Kan, Yamanaka, Helms

{"title":"Modeling And Characterization Of Si/SiO/sub 2/ Interface Roughness","authors":"Heng-Chih Lin, Kan, Yamanaka, Helms","doi":"10.1109/VLSIT.1997.623686","DOIUrl":"https://doi.org/10.1109/VLSIT.1997.623686","url":null,"abstract":"Effects of Si/SiO2 interface roughness are no longer negligible in device behavior for ULSI technology. This paper presents a comprehensive analysis of its influence on channel mobility, Fowler-Nordheim tunneling, quantum oscillation, hot carrier population, and oxide reliability. Implications of enhancement and degradation to MOS device performance and reliability are also summarized. Introduction With the advent of ULSI age, Si/SiO2 interface roughness becomes non-negligible. By analyzing the interface AFM image and electrical behavior of MOS devices, this paper presents a comprehensive modeling and characterization of interface roughness. We have found that it will fluctuate the local surface electric field [l], reduce the channel mobility [2], enhance the Fowler-Nordheim tunneling current, modify the quantum oscillation pattern, diminish the hot carrier population and slightly degrade the oxide strength. Both experimental and simulation results will be shown. Experiment The initial wafers are p-type, (100) CZ with substrate doping at 4 x 1015cm-3. LOCOS-structure MOS capacitors and MOSFETs with n+ in-situ doped poly gate and about 6 nm gate oxide were made with various deliberately roughened interfaces whose RMS roughness ranges from 0.2 nm to 4.3 nm. Hot water or BOE was used to roughen the sample either on the initial substrate or right before the gate oxidation. Interface roughness was measured by AFM on dummy wafers with oxide removed immediately after gate oxidation. Fig. 1 shows the 3D AFM images of 4 samples in this paper. MOSFET Channel Mobility We have reported that the channel mobility degradation due to interface roughness is much less severe than theoretically predicted [2]. A model is proposed here to explain this discrepancy. Fig. 2(a) shows the electron distribution and the average distance from the interface (Zezp) for various vertical E,ff by solving the 1-D Schroedinger equation and Poisson equation self-consistently. Since electrons are strongly confined to the interface for E , f f larger than 0.5 MV/cm, the perturbation theory for interface roughness scattering is not applicable for surface roughness comparable to, or larger than, Zezp. Electrons can not f ee l the full RMS roughness if the interface is very rough, but will travel conformably along the interface. Fig. 2(b) illustrates this behavior with a 2-D driftdiffusion simulation. A modification factor to channel length can be defined similar to the area factor due to interface roughness [ 11. As E, f f becomes weaker, the mobility degradation predicted by the perturbation theory is more consistent with the experimental result (Fig. 2(c)). MOS Fowler-Nordheim Tunneling Fig. 3 shows the gate oxide tunneling currents for different samples operated in the accumulation region. The current density of the roughest sample is about two orders of magnitude higher than that of the reference one. The fluctuation of the local electric field due to surface curvature is most likel","PeriodicalId":414778,"journal":{"name":"1997 Symposium on VLSI Technology","volume":"131 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-06-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131550104","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 3

A very simple trench isolation (VSTI) technology with chemo-mechanically polished (CMP) substrate Si 一个非常简单的沟槽隔离(VSTI)技术与化学机械抛光(CMP)衬底Si

1997 Symposium on VLSI Technology Pub Date : 1997-06-10 DOI: 10.1109/VLSIT.1997.623728

Park, Lee, Shin, Hong, Kang, Koh

引用次数: 1