用于无衬底偏置效应工作的高可靠0.35/spl mu/m场屏蔽体系SOI门阵列

1997 Symposium on VLSI Technology Pub Date : 1997-06-10 DOI:10.1109/VLSIT.1997.623711

Maeda, Yamaguchi, Kim, Iwamatsu, Ipposhi, Miyamoto, Hirano, Ueda, Nii, Mashiko, Maegawa, Inoue, Nishimura

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引用次数: 4

摘要

张建军，张建军，张建军，等。一种高可靠性的0.35pm场屏蔽体系SO1栅极阵列，用于无衬底偏置效应。Kim, 7: iposhi, S. Miyamoto, Y. Hirano, K. ueda *， K. Nii*， K. Mashiko*， S。Maegawa, Y. Inoue和t Nishimura ULSI实验室和*系统LSI实验室，三菱电机公司，4-1 Mizuhara，伊丹，兵库县664，日本，电话:+81-727-84-7324，传真:+81-727-80-2693

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A Highly Reliable 0.35/spl mu/m Field-shield Body-tied SOI Gate Array For Substrate-bias-effect Free Operation

A Highly Reliable 0.35pm Field-Shield Body-Tied SO1 Gate Array for Substrate-Bias-Effect Free Operation S. Maeda, Y. Yamaguchi, I.-J. Kim, 7: Iwamatsu, 7: Ipposhi, S. Miyamoto, Y. Hirano, K.Ueda*, K. Nii*, K. Mashiko*, S . Maegawa, Y. Inoue andT Nishimura ULSI Laboratory and *System LSI Laboratory, Mitsubishi Electric Corporation, 4-1 Mizuhara, Itami, Hyogo 664, JAPAN, TEL:+81-727-84-7324, FAX:+81-727-80-2693

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1997 Symposium on VLSI Technology

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