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1997 Symposium on VLSI Technology最新文献

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A 5-mask CMOS Technology 5掩模CMOS技术
1997 Symposium on VLSI Technology Pub Date : 1997-06-10 DOI: 10.1109/VLSIT.1997.623681
Onishi, Imai, Nakamura, Matsubara, Yamada, Tamura, Sakai, Horiuchi
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引用次数: 5
A Novel Copper Reflow Process Using Dual Wetting Layers 一种新型的双润湿层铜回流工艺
1997 Symposium on VLSI Technology Pub Date : 1997-06-10 DOI: 10.1109/VLSIT.1997.623693
Hirao, Satake, Kamada, Sekiguchi, Tamaki, Mayumi
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引用次数: 5
Dielectric Planarization Using Mn203 Slurry 用Mn203浆料进行介电平面化
1997 Symposium on VLSI Technology Pub Date : 1997-06-10 DOI: 10.1109/VLSIT.1997.623678
Kishii, Nakamura, Anmoto
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引用次数: 0
A 4-um/su 2/ Full-CMOS SRAM Cell Technology For 0.2-um High-performance Logic LSIs 一种用于0.2 um高性能逻辑lsi的4um / su2 /全cmos SRAM单元技术
1997 Symposium on VLSI Technology Pub Date : 1997-06-10 DOI: 10.1109/VLSIT.1997.623670
Takao, Sambonsugi, Takatsuka, Karasawa, Kawamura, Hashimoto, Takagi, Inoue, Shimizu, Yamazaki, Goto, Sugii, Miyajima, Aoyama
{"title":"A 4-um/su 2/ Full-CMOS SRAM Cell Technology For 0.2-um High-performance Logic LSIs","authors":"Takao, Sambonsugi, Takatsuka, Karasawa, Kawamura, Hashimoto, Takagi, Inoue, Shimizu, Yamazaki, Goto, Sugii, Miyajima, Aoyama","doi":"10.1109/VLSIT.1997.623670","DOIUrl":"https://doi.org/10.1109/VLSIT.1997.623670","url":null,"abstract":"","PeriodicalId":414778,"journal":{"name":"1997 Symposium on VLSI Technology","volume":"109 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-06-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115171309","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 10
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