A Simple Sub-0.3/spl mu/m CMOS Technology With Five-level Interconnect Using Al-plug And HSQ Of Low-k For High Performance Processor

Abstract

A simple sub-0.3ym CMOS technology has been developed with high performance transistors and five level interconnects. Using aluminum plug and HSQ (Hydrogen Silsesquioxane) film of low-k, the total process time is reduced by about 20% as compared with the conventional process with tungsten plug. The multimedia processor of 250MHz operation has been built on this technology. INTRODUCTION It is well known that faster transistors and multi-level interconnects will be required to maintain historic density and performance trends for high performance processor. Process steps of interconnects for total process steps are increase as generation of process technology is run. In generally, a tungsten plug(W-plug) for hole filling and AlCu materials for interconnect layer are used. Wplug is formed by blanket tungsten deposition followed by chemical mechanical polishing or etch back. This paper describes a simple logic process that meets the density and performance. This process is based on three key technologies such as faster transistor with CO salicide, aluminum plug (Al-plug), HSQ film of low-k. RESULTS AND DISCUSSION Interconnect Figure 1 shows the cross sectional view of this CMOS structure with five level interconnect. The pitches and sheet resistances of the interconnect layers are summarized in table 1. M1, M2 and M3 use a fine pitch to optimize density and capacitance for short distance interconnect. M4 and M5 use a course with thick metal to reduce parasitic resistance for long distance interconnect. In order to achieve low via resistance, good electromigration and reduction of the process time, Al-plug using high pressure[ 1][2] is adopted instead of W-plug for contact and via hole.Figure 2 shows the resistance of 3000 via chains for Al-plug and W-plug, respectively. Hole size is 0.35 x 0.35 ym2. The resistance of Al-plug is smaller by 45% than that of W-plug. Figure 3 shows comparison of the process time between Wplug and Al-plug. The process time reduction of 30% for interconnect process and 20% reduction for total process can be achieved in this Al-plug interconnect compared to the conventional W-plug interconnect. Because, aluminum PVD process using high pressure can form plug and wire at the same time. Figure 4 shows interconnect capacitances as a function of the device feature size. As the dimension shrink, the ratio of coupling capacitance to the total interconnect capacitance is increase. In this work, HSQ with low dielectric constant (k=3.6) was adopted to reduce the coupling capacitance.The inter-level dielectric was formed as follows; After the metal layer patterning, thin plasma TEOS was deposited by plasma CVD method. HSQ was applied as a spin-on layer on the plasma TEOS film. It is easy to fill gaps because HSQ has low viscosity resistance. After deposition of thick plasma TEOS, the TEOS film was planarized by CMP. Then, thin plasma TEOS was deposited to adjust the dielectric thickness. Via holes were pattemed using attenuated phase shift i-line lithography and etched using a ECR plasma oxide etch. After sputter-deposition of a TiNiTi barrier metal, AlCu film was deposited in a high pressure sputtering system. The resulting is shown in FigS. As shown in Fig.6, the parasitic coupling capacitance that metal space is 0.4pm was improved by 10% in case of HSQ spin-on process. Transistor and Performance Gate oxide thickness is 5.7 nm. Phosphorus doped polysilicon is used to form surface channel NMOS and buried channel PMOS. CoSi2 is formed on polysilicon and source/drain regions to reduce a parasitic resistance. DC characteristics of NMOS and PMOS are shown in Fig.7. Saturation drive currents are 0.47" pm @Vg=Vds=2.0V, 0.63mNpm @2SV for NMOS and 0.22" pm @2.0V, 0.32mNym @2SV for PMOS. Figure 8 shows hot canier degradation for NMOS and PMOS of 0.27pm gate length. The highest hot carrier immunity can be obtained with nitrogen implantation in the gate and the sourceldrain regions[3][4] . The stage delay for unloaded 560-stage CMOS inverter chain is 32ps at 2.5V Vcc. Figure 9 shows the comparison of the performance such as propagation delay time and active current between previous process of 0.35p.m CMOS (3.3V Vcc) and this process. It is found that the tpd is improved by about 30%, and the power consumption is reduced by 59%. Multimedia Processor These performance is characterized by actual product circuitry. Figure 10 shows multimedia processor that is integrated 300K transistors for the processor core in an 8mm2 area and I S implemented with 32K-Byte instruction and 32K-Byte data RAM onto a 6.0" x 6.2" chip and runs at 2.0V 250MHz. CONCLUSION Simple sub-0.3ym CMOS technology with AI-Plug, HSQ and high drive current has been presented. This process integration offers the process time advantage and the considerable performance advantage in comparison with conventional W-plug / oxide dielectric system. The multimedia processor of 2V 250MHz operation has been demonstrated on this process technology. REFERENCES [l]G.A.Dixit et al., IEDM Tech.Dig., P105, 1994. [2]K.Maekawa et al., Advanced Metallization [3] T.Kuroi et al., IEDM Tech.Dig., P325, 1993. [4]S.Shimizu et.al., IEDM Tech.Dig., P859, 1995. for ULSI Application, P134, 1996. 55 4-93081 3-75-1 I97 1997 Symposium on VLSl Technology Digest of Technical Papers Fig. 5 Cross sectional SEM photograph Al-Plug and HSQ.