{"title":"一个非常简单的沟槽隔离(VSTI)技术与化学机械抛光(CMP)衬底Si","authors":"Park, Lee, Shin, Hong, Kang, Koh","doi":"10.1109/VLSIT.1997.623728","DOIUrl":null,"url":null,"abstract":"A Very Simple Trench isolation (VSTI) technology with CMPed substrate-Si has been developed. VSTI has photo resist masked trench etching on a virgin Si wafer, filling with a highly conformal CVD oxide, and a CMP step down to the upper position of the Sub-Si. It shows low junction leakage current, high breakdown voltage and long TDDB characteristic on gate oxide, and perfectly flat surface. By optimizing the process, VSTI is expected to substitute the conventional isolation technology.","PeriodicalId":414778,"journal":{"name":"1997 Symposium on VLSI Technology","volume":"153 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1997-06-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"1","resultStr":"{\"title\":\"A very simple trench isolation (VSTI) technology with chemo-mechanically polished (CMP) substrate Si\",\"authors\":\"Park, Lee, Shin, Hong, Kang, Koh\",\"doi\":\"10.1109/VLSIT.1997.623728\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"A Very Simple Trench isolation (VSTI) technology with CMPed substrate-Si has been developed. VSTI has photo resist masked trench etching on a virgin Si wafer, filling with a highly conformal CVD oxide, and a CMP step down to the upper position of the Sub-Si. It shows low junction leakage current, high breakdown voltage and long TDDB characteristic on gate oxide, and perfectly flat surface. By optimizing the process, VSTI is expected to substitute the conventional isolation technology.\",\"PeriodicalId\":414778,\"journal\":{\"name\":\"1997 Symposium on VLSI Technology\",\"volume\":\"153 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1997-06-10\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"1\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"1997 Symposium on VLSI Technology\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/VLSIT.1997.623728\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"1997 Symposium on VLSI Technology","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/VLSIT.1997.623728","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
A very simple trench isolation (VSTI) technology with chemo-mechanically polished (CMP) substrate Si
A Very Simple Trench isolation (VSTI) technology with CMPed substrate-Si has been developed. VSTI has photo resist masked trench etching on a virgin Si wafer, filling with a highly conformal CVD oxide, and a CMP step down to the upper position of the Sub-Si. It shows low junction leakage current, high breakdown voltage and long TDDB characteristic on gate oxide, and perfectly flat surface. By optimizing the process, VSTI is expected to substitute the conventional isolation technology.
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