Modeling And Characterization Of Si/SiO/sub 2/ Interface Roughness

Effects of Si/SiO2 interface roughness are no longer negligible in device behavior for ULSI technology. This paper presents a comprehensive analysis of its influence on channel mobility, Fowler-Nordheim tunneling, quantum oscillation, hot carrier population, and oxide reliability. Implications of enhancement and degradation to MOS device performance and reliability are also summarized. Introduction With the advent of ULSI age, Si/SiO2 interface roughness becomes non-negligible. By analyzing the interface AFM image and electrical behavior of MOS devices, this paper presents a comprehensive modeling and characterization of interface roughness. We have found that it will fluctuate the local surface electric field [l], reduce the channel mobility [2], enhance the Fowler-Nordheim tunneling current, modify the quantum oscillation pattern, diminish the hot carrier population and slightly degrade the oxide strength. Both experimental and simulation results will be shown. Experiment The initial wafers are p-type, (100) CZ with substrate doping at 4 x 1015cm-3. LOCOS-structure MOS capacitors and MOSFETs with n+ in-situ doped poly gate and about 6 nm gate oxide were made with various deliberately roughened interfaces whose RMS roughness ranges from 0.2 nm to 4.3 nm. Hot water or BOE was used to roughen the sample either on the initial substrate or right before the gate oxidation. Interface roughness was measured by AFM on dummy wafers with oxide removed immediately after gate oxidation. Fig. 1 shows the 3D AFM images of 4 samples in this paper. MOSFET Channel Mobility We have reported that the channel mobility degradation due to interface roughness is much less severe than theoretically predicted [2]. A model is proposed here to explain this discrepancy. Fig. 2(a) shows the electron distribution and the average distance from the interface (Zezp) for various vertical E,ff by solving the 1-D Schroedinger equation and Poisson equation self-consistently. Since electrons are strongly confined to the interface for E , f f larger than 0.5 MV/cm, the perturbation theory for interface roughness scattering is not applicable for surface roughness comparable to, or larger than, Zezp. Electrons can not f ee l the full RMS roughness if the interface is very rough, but will travel conformably along the interface. Fig. 2(b) illustrates this behavior with a 2-D driftdiffusion simulation. A modification factor to channel length can be defined similar to the area factor due to interface roughness [ 11. As E, f f becomes weaker, the mobility degradation predicted by the perturbation theory is more consistent with the experimental result (Fig. 2(c)). MOS Fowler-Nordheim Tunneling Fig. 3 shows the gate oxide tunneling currents for different samples operated in the accumulation region. The current density of the roughest sample is about two orders of magnitude higher than that of the reference one. The fluctuation of the local electric field due to surface curvature is most likely responsible for this enhancement [l]. The improved tunneling efficiency from interface roughness suggests promising applications in EEPROM devices [5][6]. Relevant hot carrier injection and oxide reliability are analyzed in the later sections. Quantum Oscillation Fig. 4 shows the quantum oscillation term vs. the oxide electric field for different interface roughness. Calculation follows the one proposed in [3], With increasing interface roughness, the oscillation peak shifts left, while both the period and the amplitude decrease. This can be successfully explained by a roughness-induced-band-curving model we proposed. For rougher samples, the local electric field can be higher than the average electric field (applied voltage divided by oxide thickness), which makes the quantum oscillation shift to the low field region. Also, the electron kinetic energy becomes higher and the wavelength shorter, which decreases the oscillation period. Furthermore, the range of the electron wavelength broadens and thus coherence becomes weaker, which makes the oscillation amplitude smaller. Hot Carrier Population Interface roughness can have two effects on hot carrier population. First, the fluctuating surface field can increase the ionization rate similar to the superlattice case. Second, the lengthened surface path and additional scattering can decrease the hot carrier population. Fig. 5 compares the hot carrier effect for 4 different samples according to [4]. With increasing interface roughness, the normalized hot carrier population slightly decreases. Charge to Breakdown Controversial results have been reported regarding the effect of interface roughness on Q b d [5][7]. Based on our roughnessinduced-band-curving model corroborated by quantum oscillation in the previous section, this discrepancy can be successfully explained. With larger interface roughness, the tunneling distance for electrons is shorter but the overall voltage drop remains the same, and the average electric field after tunneling is smaller. Therefore, Q b d can be improved by interface roughness. However, roughness can also introduce additional interface defects, which in turn reduces oxide quality. The overall Q b d is determined by these two competing factors. Our experiments show no obvious relationship between Q b d and interface roughness (Fig. 6). Conclusions We have identified and modeled several significant effects of gate oxide interface roughness including the MOSFET channel mobility, the oxide tunneling current, the quantum oscillation pattern, the hot carrier effect, and the oxide quality ( Q b d ) . Device applications such as EEPROM are promising. Acknowledgments This work was performed under the financial support of SRC, ARPA, and Hitachi Ltd, Japan. The authors would like to thank Simon J. Fang for assistance on AFM measurements. [l] H-C Lin, J-F Ying, T. Yamanaka, S. J. Fang, and C. R. Helms, “Analysis of interface roughness’s effect on MOS FowlerNordheim tunneling behavior using AFM image,” in press. [2] T. Yamanaka, S. J. Fang, H-C Lin, J. P. Snyder, and C. R. Helms, “Correlation between inversion layer mobility and surface roughness measured by AFM.” IEEE EDL vo1.17, no.4, p.178-80, 1996. References 43 4-93081 3-75-1 /97 1997 Symposium on VLSl Technology Digest of Technical Papers [3] S. Zafar, Q. Liu, and E. A. Irene,"Study of tunneling current oscillation dependence on Si02 thickness and Si roughness at the Si/SiOz interface." JVST-A, vo1.13, no. I , p. 47-53, 1995. 141 T. Y. Chan, P. K . KO, and C. Hu, "A simple method to characterize substrate current in MOSFETs", IEEE EDL, No. 12, p.505-507, 1984. [5] Y. Fong, A.T.-T. Wu, and C. Hu, "Oxides grown on textured single-crystal silicon-dependence on process and application of EEPROMs.", IEEEED, vo1.37, no.3, pt.1, p. 583-90, 1990. [6] P-W Wang, T-K Ku; H-P Su, G. Hong, and H-C Cheng, "Excellent emission characteristics of tunneling oxides formed using ultrathin silicon films for ffash memory devices". JJAP, vo1.35, no.6A, p.3369-73, 1996. [7] M. Miyashita, M. Itano, T. Imaoka, I. Kawanabe, and T. Ohmi, "Dependence of thin oxide films quality on surface microroughness." 1991 Symp. on VLSI Tech., Tokyo, Japan. p.45-6. Figure I: 3D view of AFM images (a)-(d) for samples A-D, respectively. The scan size is lpm x 1pm. Here an area of lOOnm x lOOnm is shown for a better view of the fine features. The RMS roughness ranges from 0.2nm (d) to 4.3nm (b).