Boron Implanted Shallow Junction Formation By High-temperature/ Short-time/high-ramping-rate(400/spl deg/C/sec) RTA

Abstract

This paper proposes a novel 50nm-depth shallow junction formation for realizing low SD-extension resistance in deep sub-quarter micron PMOS-FETs. In this technology, the extension is fabricated by Ge'(5keV) pre-amorphizised lowenergy B'( 1 keV) implantation, followed by optimized RTA condition (1 100°C for 50msec with ramping-rate 400"C/sec). It has become apparent that this optimized condition yields the lower resistance-limit(300~/sq) for 50nm-depth junction, when using ion implantation process. S/D series resistance for the O.15ym-PMOS(W= IOym) fabricated by this technology is reduced to 140R. This result shows that high-performance deep sub-quarter micron CMOS-FETs are realized by the optimization of ion implantation and/or RTA process.