基于升压线技术的多级NAND闪存单元快速并行编程

Choi, Kim, Shin, Mang, Ahn
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引用次数: 3

摘要

采用这种编程方法,程序速度可达300us,相当于单比特NAND单元的速度,是实现多级单元(MLC)技术所必不可少的。采用升压线的并行编程显著降低了闪存的比特成本[j]。然而,高MLC需要20以上编程电压的高编程电压,编程时间和V较长,编程时间较长等缺点[11]。增加干扰。我们在过去的研究中证明了升压板多级单元特性NAND闪存技术提高了程序速度并消除了程序干扰[2]。本文提出了一种新的MLC NAND快速并行编程方法。通过在单元串上增加升压线,每个NAND串的程序速度可以通过升压线的偏置来控制。这种方法本质上是通过控制单个存储单元的程序电压,在给定的编程时间内获得不同的单元阈值电压(v th)。从而实现了具有可与单位NAND单元相媲美的编程速度和可靠性的四级MLC。从图4可以看出,四电平单元阵列(4k位)的测量Vth值分布紧密,小于0.5 V。擦除特性几乎与Vth电平无关,如图5所示。由于编程电压高、编程时间长,传统MLC中的非选择单元受到的干扰较大。而采用升压线后,在没有Program电压扰动(Vpgm应力)的情况下,Vpws区较宽,且在通电压小于7 V时,Vpgm应力为Vpass应力,如图6所示。Vpgm应激完全消失是由于增强细胞系增强了程序抑制细胞的自我促进作用[2]。由于Vth窗口的减少,在MLC中有足够的传感裕度是很重要的。“开”时的电池串电流最小,电池结构和运行方式的差异最小
本文章由计算机程序翻译,如有差异,请以英文原文为准。
Fast Parallel Programming Of Multi-level NAND Flash Memory Cells Using The Booster-line Technology
Introduction With this programming method, a program speed of 300 ,us, which is equivalent to that of the single bit NAND cell, is The Multi-Level Cell (MLC) technology is essential in achieved. The parallel programming with booster-lines significantly reducing the bit cost of flash memories [I]. results in a significant improvement over the conventional The MLC, however, has drawbacks such as high MLC which requires a high programming voltage of over 20 programming voltage, longer programming time and V and prolonged programming time [ 11. increased disturbances. We demonstrated in the Dast that the booster plate Multi-Level Cell Characteristics NAND flash technology enhances the program speed and eliminates the program disturbance [2]. In this paper, we report a new fast parallel programming method for MLC NAND. With the addition of booster-lines to the cell strings, the program speed of each NAND string can be controlled by the booster-line bias. This method in essence is to obtain different cell threshold voltages ( v t h ) at a given programming time by controlling the program voltage of individual memory cells. Thus the four-level MLC with programming speed and reliability comparable to those of the single bit NAND cell is achieved. Fig. 4 shows that the measured Vth’s of the four-level cell array (4k bits) have tight distributions of less than 0.5 V. The erase characteristics are almost independent of the Vth levels as shown in Fig. 5 . Due to high programming voltage and long programming time, unselected cells in conventional MLC’s are exposed to increased disturbances. The adoption of booster-lines, however, results in a wide Vpws zone without Program voltage disturbance (Vpgm stress) and Vpass stress at pass voltage less than 7 V, as shown in Fig. 6. The complete disappearence of the Vpgm stress is caused by the enhanced self-boosting action in program inhibited cells by boosterlines [2]. It is important to have enough sensing margin in MLC because of the reduced Vth windows. The “ON” cell string current is the smallest when the difference between the cell Cell Structure and Operation
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