{"title":"基于升压线技术的多级NAND闪存单元快速并行编程","authors":"Choi, Kim, Shin, Mang, Ahn","doi":"10.1109/VLSIT.1997.623697","DOIUrl":null,"url":null,"abstract":"Introduction With this programming method, a program speed of 300 ,us, which is equivalent to that of the single bit NAND cell, is The Multi-Level Cell (MLC) technology is essential in achieved. The parallel programming with booster-lines significantly reducing the bit cost of flash memories [I]. results in a significant improvement over the conventional The MLC, however, has drawbacks such as high MLC which requires a high programming voltage of over 20 programming voltage, longer programming time and V and prolonged programming time [ 11. increased disturbances. We demonstrated in the Dast that the booster plate Multi-Level Cell Characteristics NAND flash technology enhances the program speed and eliminates the program disturbance [2]. In this paper, we report a new fast parallel programming method for MLC NAND. With the addition of booster-lines to the cell strings, the program speed of each NAND string can be controlled by the booster-line bias. This method in essence is to obtain different cell threshold voltages ( v t h ) at a given programming time by controlling the program voltage of individual memory cells. Thus the four-level MLC with programming speed and reliability comparable to those of the single bit NAND cell is achieved. Fig. 4 shows that the measured Vth’s of the four-level cell array (4k bits) have tight distributions of less than 0.5 V. The erase characteristics are almost independent of the Vth levels as shown in Fig. 5 . Due to high programming voltage and long programming time, unselected cells in conventional MLC’s are exposed to increased disturbances. The adoption of booster-lines, however, results in a wide Vpws zone without Program voltage disturbance (Vpgm stress) and Vpass stress at pass voltage less than 7 V, as shown in Fig. 6. The complete disappearence of the Vpgm stress is caused by the enhanced self-boosting action in program inhibited cells by boosterlines [2]. It is important to have enough sensing margin in MLC because of the reduced Vth windows. The “ON” cell string current is the smallest when the difference between the cell Cell Structure and Operation","PeriodicalId":414778,"journal":{"name":"1997 Symposium on VLSI Technology","volume":"123 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1997-06-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"3","resultStr":"{\"title\":\"Fast Parallel Programming Of Multi-level NAND Flash Memory Cells Using The Booster-line Technology\",\"authors\":\"Choi, Kim, Shin, Mang, Ahn\",\"doi\":\"10.1109/VLSIT.1997.623697\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"Introduction With this programming method, a program speed of 300 ,us, which is equivalent to that of the single bit NAND cell, is The Multi-Level Cell (MLC) technology is essential in achieved. The parallel programming with booster-lines significantly reducing the bit cost of flash memories [I]. results in a significant improvement over the conventional The MLC, however, has drawbacks such as high MLC which requires a high programming voltage of over 20 programming voltage, longer programming time and V and prolonged programming time [ 11. increased disturbances. We demonstrated in the Dast that the booster plate Multi-Level Cell Characteristics NAND flash technology enhances the program speed and eliminates the program disturbance [2]. In this paper, we report a new fast parallel programming method for MLC NAND. With the addition of booster-lines to the cell strings, the program speed of each NAND string can be controlled by the booster-line bias. This method in essence is to obtain different cell threshold voltages ( v t h ) at a given programming time by controlling the program voltage of individual memory cells. Thus the four-level MLC with programming speed and reliability comparable to those of the single bit NAND cell is achieved. Fig. 4 shows that the measured Vth’s of the four-level cell array (4k bits) have tight distributions of less than 0.5 V. The erase characteristics are almost independent of the Vth levels as shown in Fig. 5 . Due to high programming voltage and long programming time, unselected cells in conventional MLC’s are exposed to increased disturbances. The adoption of booster-lines, however, results in a wide Vpws zone without Program voltage disturbance (Vpgm stress) and Vpass stress at pass voltage less than 7 V, as shown in Fig. 6. The complete disappearence of the Vpgm stress is caused by the enhanced self-boosting action in program inhibited cells by boosterlines [2]. It is important to have enough sensing margin in MLC because of the reduced Vth windows. The “ON” cell string current is the smallest when the difference between the cell Cell Structure and Operation\",\"PeriodicalId\":414778,\"journal\":{\"name\":\"1997 Symposium on VLSI Technology\",\"volume\":\"123 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1997-06-10\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"3\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"1997 Symposium on VLSI Technology\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/VLSIT.1997.623697\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"1997 Symposium on VLSI Technology","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/VLSIT.1997.623697","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Fast Parallel Programming Of Multi-level NAND Flash Memory Cells Using The Booster-line Technology
Introduction With this programming method, a program speed of 300 ,us, which is equivalent to that of the single bit NAND cell, is The Multi-Level Cell (MLC) technology is essential in achieved. The parallel programming with booster-lines significantly reducing the bit cost of flash memories [I]. results in a significant improvement over the conventional The MLC, however, has drawbacks such as high MLC which requires a high programming voltage of over 20 programming voltage, longer programming time and V and prolonged programming time [ 11. increased disturbances. We demonstrated in the Dast that the booster plate Multi-Level Cell Characteristics NAND flash technology enhances the program speed and eliminates the program disturbance [2]. In this paper, we report a new fast parallel programming method for MLC NAND. With the addition of booster-lines to the cell strings, the program speed of each NAND string can be controlled by the booster-line bias. This method in essence is to obtain different cell threshold voltages ( v t h ) at a given programming time by controlling the program voltage of individual memory cells. Thus the four-level MLC with programming speed and reliability comparable to those of the single bit NAND cell is achieved. Fig. 4 shows that the measured Vth’s of the four-level cell array (4k bits) have tight distributions of less than 0.5 V. The erase characteristics are almost independent of the Vth levels as shown in Fig. 5 . Due to high programming voltage and long programming time, unselected cells in conventional MLC’s are exposed to increased disturbances. The adoption of booster-lines, however, results in a wide Vpws zone without Program voltage disturbance (Vpgm stress) and Vpass stress at pass voltage less than 7 V, as shown in Fig. 6. The complete disappearence of the Vpgm stress is caused by the enhanced self-boosting action in program inhibited cells by boosterlines [2]. It is important to have enough sensing margin in MLC because of the reduced Vth windows. The “ON” cell string current is the smallest when the difference between the cell Cell Structure and Operation