A 0.18/spl mu/m CMOS Process Using Nitrogen Profile-engineered Gate Dielectrics

A novel gate dielectric, with nitrogen confined within the top 0.7nm of the oxide surface, has been demonstrated in a 0.18pm CMOS process. High nitrogen concentrations (>lo%), incorporated by remote plasma nitridation (RPN), are demonstrated to suppress boron penetration in 4.0nm gate dielectrics with no degradation in n-ch or p-ch mobility. Drive currents with the RPN oxide were equivalent to, or exceeded those obtained with an Si02 control. Various gate doping schemes were explored to quantify contributions of poly depletion and Rsd on device performance. It was found that poly depletion accounts for less than one-half of the drive current improvement when PMOS source/drain doping is increased.