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2010 Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems (SiRF)最新文献

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A 1.9V 25GHz SiGe static frequency dividers with clock-sharing topology 时钟共享拓扑的1.9V 25GHz SiGe静态分频器
2010 Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems (SiRF) Pub Date : 2010-03-01 DOI: 10.1109/SMIC.2010.5422950
Weiran Cai, F. Ellinger, J. Carls
{"title":"A 1.9V 25GHz SiGe static frequency dividers with clock-sharing topology","authors":"Weiran Cai, F. Ellinger, J. Carls","doi":"10.1109/SMIC.2010.5422950","DOIUrl":"https://doi.org/10.1109/SMIC.2010.5422950","url":null,"abstract":"A novel low-voltage, high-speed static divider topology using shared clock-transistors is proposed. The divide-by-2 is implemented in 0.18 ¿m 60 GHz-fT SiGe BiCMOS technology. At 1.9 V × 9 mA supply power of the divider core, an operation frequency of up to 25 GHz was measured. Compared to the conventional D flip-flop architecture, at similar speed, a reduction of 34% in supply power is enabled.","PeriodicalId":404957,"journal":{"name":"2010 Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems (SiRF)","volume":"10 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117226987","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Design and analysis of a W-Band detector in 0.18-µm SiGe BiCMOS 0.18µm SiGe BiCMOS中w波段探测器的设计与分析
2010 Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems (SiRF) Pub Date : 2010-03-01 DOI: 10.1109/SMIC.2010.5422987
Le Zheng, L. Gilreath, V. Jain, P. Heydari
{"title":"Design and analysis of a W-Band detector in 0.18-µm SiGe BiCMOS","authors":"Le Zheng, L. Gilreath, V. Jain, P. Heydari","doi":"10.1109/SMIC.2010.5422987","DOIUrl":"https://doi.org/10.1109/SMIC.2010.5422987","url":null,"abstract":"This paper presents the analysis, design and implementation of a millimeter-wave W-band power detector. Fabricated in a 0.18-µm SiGe BiCMOS technology, the detector circuit exhibits a responsivity of 91 kV/W, a noise equivalent power of 0.5 pW/Hz, and a noise figure of 29 dB. The power dissipation of the detector is 75 µW. Reasonable agreement between simulations and measurements is obtained. To the authors' best knowledge, the detector in this work achieves the highest responsivity reported to date for any solid-state W-band detector.","PeriodicalId":404957,"journal":{"name":"2010 Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems (SiRF)","volume":"38 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124791358","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 22
Modeling of substrate noise in monolithic integrated circuits 单片集成电路中衬底噪声的建模
2010 Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems (SiRF) Pub Date : 2010-03-01 DOI: 10.1109/SMIC.2010.5422981
G. Manetas, A. Cangellaris
{"title":"Modeling of substrate noise in monolithic integrated circuits","authors":"G. Manetas, A. Cangellaris","doi":"10.1109/SMIC.2010.5422981","DOIUrl":"https://doi.org/10.1109/SMIC.2010.5422981","url":null,"abstract":"A convenient model is presented for the expedient calculation of semiconductor substrate-induced noise coupling under quasi-static conditions. The proposed model is motivated by the desire to provide for a quick means for predictive assessment of substrate noise levels with computational efficiency appropriate for noise-aware floor-planning and routing considerations early in the design phase. While computationally efficient, the quasi-static attributes of the model call for an assessment of the frequency range of its validity. To provide for this, a full-wave electrodynamic model is used to derive a quantity, termed dynamic factor, as a means to assess the accuracy of the quasi-static model versus frequency and substrate properties.","PeriodicalId":404957,"journal":{"name":"2010 Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems (SiRF)","volume":"53 7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125054747","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Analog/RF performance of sub-100 nm SOI MOSFETs with non-classical gate-source/drain underlap channel design 采用非经典栅极-源极-漏极下迭通道设计的亚100nm SOI mosfet模拟/射频性能
2010 Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems (SiRF) Pub Date : 2010-03-01 DOI: 10.1109/SMIC.2010.5422943
A. Kranti, Rashmi, S. Burignat, J. Raskin, G. A. Armstrong
{"title":"Analog/RF performance of sub-100 nm SOI MOSFETs with non-classical gate-source/drain underlap channel design","authors":"A. Kranti, Rashmi, S. Burignat, J. Raskin, G. A. Armstrong","doi":"10.1109/SMIC.2010.5422943","DOIUrl":"https://doi.org/10.1109/SMIC.2010.5422943","url":null,"abstract":"In this work, we analyze the potential of non-overlap (also known as underlap) source/drain (S/D) channel architecture to improve analog/RF performance metrics of sub-100 nm Ultra Thin Body BOX (UTBB) SOI MOSFETs. It is shown that underlap S/D design results in higher voltage gain (A<inf>VO</inf>) and cut-off frequency (f<inf>T</inf>) along with a broader analog ‘sweet spot’ in nanoscale MOSFETs thus offering new possibilities for analog/RF scaling below 60 nm. The advantages offered by underlap channel design are not limited to lower current levels (∼ 10 µA/µm) but extend up to 100 µA/µm which corresponds to optimum A<inf>VO</inf> and f<inf>T</inf> performance for most circuit applications. For shorter gate length devices, underlap design results in an impressive 20% improvement in f<inf>T</inf> along with a 2 fold enhancement in A<inf>VO</inf>. This work provides new opportunities for realizing future low-power analog/RF design with underlap UTBB MOSFETs.","PeriodicalId":404957,"journal":{"name":"2010 Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems (SiRF)","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124589074","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 17
Fully balanced 60 GHz LNA with 37 % bandwidth, 3.8 dB NF, 10 dB gain and constant group delay over 6 GHz bandwidth 全平衡60ghz LNA，带宽37%，NF 3.8 dB，增益10db，在6ghz带宽上具有恒定的组延迟
2010 Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems (SiRF) Pub Date : 2010-03-01 DOI: 10.1109/SMIC.2010.5422843
E. Janssen, R. Mahmoudi, E. van der Heijden, P. Sakian, A. de Graauw, R. Pijper, A. V. van Roermund
{"title":"Fully balanced 60 GHz LNA with 37 % bandwidth, 3.8 dB NF, 10 dB gain and constant group delay over 6 GHz bandwidth","authors":"E. Janssen, R. Mahmoudi, E. van der Heijden, P. Sakian, A. de Graauw, R. Pijper, A. V. van Roermund","doi":"10.1109/SMIC.2010.5422843","DOIUrl":"https://doi.org/10.1109/SMIC.2010.5422843","url":null,"abstract":"This paper presents a two-stage fully integrated 60 GHz differential Low Noise Amplifier implemented in a TSMC bulk CMOS 65 nm technology. Implementation of a voltage-voltage feedback enables the neutralization of the Miller capacitance and the achievement of flat gain with a deviation of ± 0.25 dB over the entire 6 GHz bandwidth. It features a transducer gain (Gt) of 10 dB along with a noise figure (NF) of 3.8 dB, NFmin of 3.7 dB and a constant delay time. IIP3 is 4 dBm. It consumes 35 mW from a 1.2 V supply and only occupies 330 × 170 µm.","PeriodicalId":404957,"journal":{"name":"2010 Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems (SiRF)","volume":"14 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126863007","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 19
Efficient polysilicon passivation layer for crosstalk reduction in high-resistivity SOI substrates 高电阻率SOI衬底中减少串扰的高效多晶硅钝化层
2010 Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems (SiRF) Pub Date : 2010-03-01 DOI: 10.1109/SMIC.2010.5422973
K. Ben Ali, C. Roda Neve, A. Gharsallah, J. Raskin
{"title":"Efficient polysilicon passivation layer for crosstalk reduction in high-resistivity SOI substrates","authors":"K. Ben Ali, C. Roda Neve, A. Gharsallah, J. Raskin","doi":"10.1109/SMIC.2010.5422973","DOIUrl":"https://doi.org/10.1109/SMIC.2010.5422973","url":null,"abstract":"Substrate crosstalk and RF losses in HR-SOI, and the introduction of a stabilized polysilicon layer are deeply investigated. A new equivalent lumped circuit to model different substrate types and resistivities, and SiO2-Si interface qualities is proposed and validated by simulation and experimental data. It is also valid to model the introduction of high-trap density at the interface, and it successfully explains the higher measured values of substrate crosstalk at low frequencies for HR-Si substrates.","PeriodicalId":404957,"journal":{"name":"2010 Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems (SiRF)","volume":"44 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114876999","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 7
Mixed-signal techniques in mm-wave range for 100 Gbit decision feedback equalizer 100gb决策反馈均衡器的毫米波混合信号技术
2010 Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems (SiRF) Pub Date : 2010-03-01 DOI: 10.1109/SMIC.2010.5422959
A. Awny, A. Thiede, M. Elkhouly, J. Borngraber, F. Korndorfer, J. Scheytt
{"title":"Mixed-signal techniques in mm-wave range for 100 Gbit decision feedback equalizer","authors":"A. Awny, A. Thiede, M. Elkhouly, J. Borngraber, F. Korndorfer, J. Scheytt","doi":"10.1109/SMIC.2010.5422959","DOIUrl":"https://doi.org/10.1109/SMIC.2010.5422959","url":null,"abstract":"The design of very high speed broadband latched comparators and D flip-flops in 0.13 ¿m SiGe bipolar technology is presented. The latched comparators are used as a broadband front-end of a 1-tap decision feedback equalizer (DFE) for 100 Gb/s optical communication. Techniques for evaluating the bandwidth of the differential voltage gain from the single ended S-parameter measurements of the designed comparators up to 110 GHz are presented. The measurement results show a 3 dB bandwidth of about 70.5 GHz for the differential voltage gain. A static frequency divider is also fabricated to evaluate the performance of the designed D flip-flops used in the DFE in time domain and operates in measurement up to 86 GHz while consuming power as low as 96.25 mW per latch. A half rate parallel look-ahead architecture is used for the implementation of the DFE.","PeriodicalId":404957,"journal":{"name":"2010 Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems (SiRF)","volume":"51 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130957258","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Characterization of an embedded RF-MEMS switch 嵌入式RF-MEMS开关的特性研究
2010 Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems (SiRF) Pub Date : 2010-03-01 DOI: 10.1109/SMIC.2010.5422816
M. Kaynak, K. Ehwald, R. Scholz, F. Korndorfer, C. Wipf, Y.M. Sun, B. Tillack, S. Zihir, Y. Gurbuz
{"title":"Characterization of an embedded RF-MEMS switch","authors":"M. Kaynak, K. Ehwald, R. Scholz, F. Korndorfer, C. Wipf, Y.M. Sun, B. Tillack, S. Zihir, Y. Gurbuz","doi":"10.1109/SMIC.2010.5422816","DOIUrl":"https://doi.org/10.1109/SMIC.2010.5422816","url":null,"abstract":"An RF-MEMS capacitive switch for mm-wave integrated circuits, embedded in the BEOL of 0.25 ¿m BiCMOS process, has been characterized. First, a mechanical model based on Finite-Element-Method (FEM) was developed by taking the residual stress of the thin film membrane into account. The pull-in voltage and the capacitance values obtained with the mechanical model agree very well with the measured values. Moreover, S-parameters were extracted using Electromagnetic (EM) solver. The data observed in this way also agree well with the experimental ones measured up to 110 GHz. The developed RF model was applied to a transmit/receive (T/R) antenna switch design. The results proved the feasibility of using the FEM model in circuit simulations for the development of RF-MEMS switch embedded, single-chip multi-band RF ICs.","PeriodicalId":404957,"journal":{"name":"2010 Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems (SiRF)","volume":"464 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133399244","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 26
A 53–64-GHz SiGe up-conversion mixer with 4-GHz IF bandwidth 具有4 ghz中频带宽的53 - 64 ghz SiGe上转换混频器
2010 Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems (SiRF) Pub Date : 2010-03-01 DOI: 10.1109/SMIC.2010.5422955
M. Ko, H. Rucker, W. Choi
{"title":"A 53–64-GHz SiGe up-conversion mixer with 4-GHz IF bandwidth","authors":"M. Ko, H. Rucker, W. Choi","doi":"10.1109/SMIC.2010.5422955","DOIUrl":"https://doi.org/10.1109/SMIC.2010.5422955","url":null,"abstract":"A Gilbert-cell direct up-conversion mixer is realized for 57-64-GHz unlicensed-band applications. The mixer with on-chip stacked inductors and LO, RF baluns is fabricated in 0.25-¿m SiGe:C BiCMOS technology. The fabricated mixer achieves conversion gain of 4 ± 1.5 dB and 5 ± 1 dB for upper and lower sideband, respectively, in frequency range from 53 to 64 GHz. The LO-to-RF isolation is higher than 30 dB. The mixer has IF bandwidth of 4 GHz, and the output-referred 1-dB compression point of -9.5 dBm. It occupies a chip area of 0.46 mm × 0.46 mm and consumes 10 mA with supply voltage of 2.5 V.","PeriodicalId":404957,"journal":{"name":"2010 Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems (SiRF)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124299981","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 7
Scalable transformer model based on ladder topological equivalent circuit for Si RFICs 基于阶梯拓扑等效电路的硅射频集成电路可扩展变压器模型
2010 Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems (SiRF) Pub Date : 2010-03-01 DOI: 10.1109/SMIC.2010.5422954
N. Shiramizu, T. Masuda, Takahiro Nakamura, K. Washio
{"title":"Scalable transformer model based on ladder topological equivalent circuit for Si RFICs","authors":"N. Shiramizu, T. Masuda, Takahiro Nakamura, K. Washio","doi":"10.1109/SMIC.2010.5422954","DOIUrl":"https://doi.org/10.1109/SMIC.2010.5422954","url":null,"abstract":"Scalable modeling methodology of on-chip spiral interleaved transformer is proposed. The novel equivalent circuit based on ladder topology is composed of lumped elements and their parameters are completely derived from the physical structure. The circuit topology enables to express the inductive and capacitive coupling effect between half turn segmented wires accurately. The circuit also contributes to obtain the scalability related to wire width/space, length, and diameter. In this model, coupling capacitance between adjacent wires is given by considering parallel paths through oxide layer and Si substrate. The model simulation result matched the measurement result of a fabricated transformer TEG with the error less than 5% for wide frequency range up-to quasi-millimeter wave band.","PeriodicalId":404957,"journal":{"name":"2010 Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems (SiRF)","volume":"103 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116297600","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 7
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