A 1.9V 25GHz SiGe static frequency dividers with clock-sharing topology

Abstract

A novel low-voltage, high-speed static divider topology using shared clock-transistors is proposed. The divide-by-2 is implemented in 0.18 ¿m 60 GHz-fT SiGe BiCMOS technology. At 1.9 V × 9 mA supply power of the divider core, an operation frequency of up to 25 GHz was measured. Compared to the conventional D flip-flop architecture, at similar speed, a reduction of 34% in supply power is enabled.