100gb决策反馈均衡器的毫米波混合信号技术

2010 Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems (SiRF) Pub Date : 2010-03-01 DOI:10.1109/SMIC.2010.5422959

A. Awny, A. Thiede, M. Elkhouly, J. Borngraber, F. Korndorfer, J. Scheytt

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引用次数: 2

摘要

介绍了一种采用0.13 μ m SiGe双极技术的超高速宽带锁存比较器和D触发器的设计。锁存比较器被用作100gb /s光通信的1分路决策反馈均衡器(DFE)的宽带前端。本文介绍了从所设计的比较器的单端s参数测量到110 GHz的差分电压增益带宽的评估技术。测量结果表明，差分电压增益约为70.5 GHz，带宽为3db。此外，还制作了一个静态分频器来评估所设计的D触发器用于DFE的时域性能，其工作频率高达86 GHz，每个锁存器的功耗低至96.25 mW。DFE的实现采用了半速率并行预查架构。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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Mixed-signal techniques in mm-wave range for 100 Gbit decision feedback equalizer

The design of very high speed broadband latched comparators and D flip-flops in 0.13 ¿m SiGe bipolar technology is presented. The latched comparators are used as a broadband front-end of a 1-tap decision feedback equalizer (DFE) for 100 Gb/s optical communication. Techniques for evaluating the bandwidth of the differential voltage gain from the single ended S-parameter measurements of the designed comparators up to 110 GHz are presented. The measurement results show a 3 dB bandwidth of about 70.5 GHz for the differential voltage gain. A static frequency divider is also fabricated to evaluate the performance of the designed D flip-flops used in the DFE in time domain and operates in measurement up to 86 GHz while consuming power as low as 96.25 mW per latch. A half rate parallel look-ahead architecture is used for the implementation of the DFE.

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2010 Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems (SiRF)

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