Modeling of substrate noise in monolithic integrated circuits

Abstract

A convenient model is presented for the expedient calculation of semiconductor substrate-induced noise coupling under quasi-static conditions. The proposed model is motivated by the desire to provide for a quick means for predictive assessment of substrate noise levels with computational efficiency appropriate for noise-aware floor-planning and routing considerations early in the design phase. While computationally efficient, the quasi-static attributes of the model call for an assessment of the frequency range of its validity. To provide for this, a full-wave electrodynamic model is used to derive a quantity, termed dynamic factor, as a means to assess the accuracy of the quasi-static model versus frequency and substrate properties.