Analog/RF performance of sub-100 nm SOI MOSFETs with non-classical gate-source/drain underlap channel design

Abstract

In this work, we analyze the potential of non-overlap (also known as underlap) source/drain (S/D) channel architecture to improve analog/RF performance metrics of sub-100 nm Ultra Thin Body BOX (UTBB) SOI MOSFETs. It is shown that underlap S/D design results in higher voltage gain (AVO) and cut-off frequency (fT) along with a broader analog ‘sweet spot’ in nanoscale MOSFETs thus offering new possibilities for analog/RF scaling below 60 nm. The advantages offered by underlap channel design are not limited to lower current levels (∼ 10 µA/µm) but extend up to 100 µA/µm which corresponds to optimum AVO and fT performance for most circuit applications. For shorter gate length devices, underlap design results in an impressive 20% improvement in fT along with a 2 fold enhancement in AVO. This work provides new opportunities for realizing future low-power analog/RF design with underlap UTBB MOSFETs.