时钟共享拓扑的1.9V 25GHz SiGe静态分频器

2010 Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems (SiRF) Pub Date : 2010-03-01 DOI:10.1109/SMIC.2010.5422950

Weiran Cai, F. Ellinger, J. Carls

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引用次数: 0

摘要

提出了一种基于共享时钟晶体管的新型低压高速静态分频拓扑结构。除2是在0.18¿m 60 GHz-fT SiGe BiCMOS技术实现的。在1.9 V × 9 mA的分压器磁芯供电时，测量到的工作频率高达25 GHz。与传统的D触发器架构相比，在相同的速度下，电源功耗降低了34%。

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A 1.9V 25GHz SiGe static frequency dividers with clock-sharing topology

A novel low-voltage, high-speed static divider topology using shared clock-transistors is proposed. The divide-by-2 is implemented in 0.18 ¿m 60 GHz-fT SiGe BiCMOS technology. At 1.9 V × 9 mA supply power of the divider core, an operation frequency of up to 25 GHz was measured. Compared to the conventional D flip-flop architecture, at similar speed, a reduction of 34% in supply power is enabled.

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2010 Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems (SiRF)

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