1998 Symposium on VLSI Technology Digest of Technical Papers (Cat. No.98CH36216)最新文献

A self-aligned STI process integration for low cost and highly reliable 1 Gbit flash memories 一种用于低成本、高可靠性1gbit快闪记忆体的自对准STI制程整合

1998 Symposium on VLSI Technology Digest of Technical Papers (Cat. No.98CH36216) Pub Date : 1998-06-09 DOI: 10.1109/VLSIT.1998.689216

Y. Takeuchi, K. Shimizu, K. Narita, E. Kamiya, T. Yaegashi, K. Amemiya, S. Aritome

引用次数: 7

Highly scalable and fully logic compatible SRAM cell technology with metal damascene process and W local interconnect 高度可扩展和完全逻辑兼容的SRAM单元技术与金属damascene工艺和W本地互连

1998 Symposium on VLSI Technology Digest of Technical Papers (Cat. No.98CH36216) Pub Date : 1998-06-09 DOI: 10.1109/VLSIT.1998.689200

M. Inohara, H. Oyamatsu, Y. Unno, Y. Fukaura, S. Goto, Y. Egi, M. Kinugawa

{"title":"Highly scalable and fully logic compatible SRAM cell technology with metal damascene process and W local interconnect","authors":"M. Inohara, H. Oyamatsu, Y. Unno, Y. Fukaura, S. Goto, Y. Egi, M. Kinugawa","doi":"10.1109/VLSIT.1998.689200","DOIUrl":"https://doi.org/10.1109/VLSIT.1998.689200","url":null,"abstract":"For future SRAM cells, scalability with operation voltage reduction as well as device dimensions is very desirable. Moreover, higher compatibility with advanced logic process will become important more and more due to requirements from high performance SRAM-embedded LSIs such as RISC chips or multimedia LSIs. However, although a lot of candidates for the future SRAM cell have been reported, there have been few paper discussing systematically what kind of cell technology can be the main stream for future SRAM cells. In this paper, a SRAM technology with high scalability and excellent logic process compatibility has been proposed as a result of systematic consideration. In this technology, 6Tr. cell with small parasitic resistance is chosen for high cell stability under low operation voltage. W local interconnect (LI) is also implemented to realize smaller cell size with reduced bit-line capacitance. Moreover, cell layout as well as fabrication process is designed to be preferable for metal damascene process. With using damascene technology, W-LI can be fabricated by simple contact W-plug process simultaneously. As a result, highly scalable 6Tr. cell, which can be fabricated by an advanced logic process without any photo mask or process step increase, has been obtained. In order to demonstrate this cell technology, a 0.25 /spl mu/m SRAM cell with the cell size of 3.9 /spl mu/m/sup 2/ was fabricated and evaluated. Moreover, the scalability of this cell technology down to 0.15 /spl mu/m generation was confirmed by simulation.","PeriodicalId":402365,"journal":{"name":"1998 Symposium on VLSI Technology Digest of Technical Papers (Cat. No.98CH36216)","volume":"83 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-06-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122632343","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 3

A high-performance sub-0.25 /spl mu/m CMOS technology with multiple thresholds and copper interconnects 一种高性能的低于0.25 /spl μ m的CMOS技术，具有多个阈值和铜互连

1998 Symposium on VLSI Technology Digest of Technical Papers (Cat. No.98CH36216) Pub Date : 1998-06-09 DOI: 10.1109/VLSIT.1998.689182

L. Su, R. Schulz, J. Adkisson, K. Beyer, G. Biery, William J. Cote, Emmanuel F. Crabbe, Daniel C. Edelstein, J. Ellis-Monaghan, E. Eld, D. Foster, R. Gehres, R. Goldblatt, N. Greco, C. Guenther, John E. Heidenreich, J. Herman, D. Kiesling, L. Lin, S.-H. Lo, J. McKenna, C. Megivern, H. Ng, J. Oberschmidt, A. Ray, Norman J. Rohrer, K. Tallman, T. Wagner, B. Davari

引用次数: 32

Electromigration of submicron Damascene copper interconnects 亚微米大马士革铜互连的电迁移

1998 Symposium on VLSI Technology Digest of Technical Papers (Cat. No.98CH36216) Pub Date : 1998-06-09 DOI: 10.1109/VLSIT.1998.689238

C. Ryu, Kee-Won Kwon, A. Loke, V.M. Dubin, R.A. Kavari, G. Ray, S. Wong

引用次数: 24

A novel air gap integration scheme for multi-level interconnects using self-aligned via plugs 一种基于自对准通孔插头的多级互连气隙集成方案

1998 Symposium on VLSI Technology Digest of Technical Papers (Cat. No.98CH36216) Pub Date : 1998-06-09 DOI: 10.1109/VLSIT.1998.689193

T. Ueda, E. Tamaoka, K. Yamashita, N. Aoi, S. Mayumi

引用次数: 16

A scalable single-transistor/single-capacitor memory cell structure characterized by an angled-capacitor layout for megabit FeRAMs 一种可扩展的单晶体管/单电容存储单元结构，其特点是用于兆位feram的角度电容布局

1998 Symposium on VLSI Technology Digest of Technical Papers (Cat. No.98CH36216) Pub Date : 1998-06-09 DOI: 10.1109/VLSIT.1998.689227

T. Kachi, K. Shoji, H. Yamashita, T. Kisu, K. Torii, T. Kumihashi, Y. Fujisaki, N. Yokoyama

引用次数: 2

A dynamic depletion SOI MOSFET model for SPICE 用于SPICE的动态耗尽型SOI MOSFET模型

1998 Symposium on VLSI Technology Digest of Technical Papers (Cat. No.98CH36216) Pub Date : 1998-06-09 DOI: 10.1109/VLSIT.1998.689222

D. Sinitsky, S. Fung, S. Tang, P. Su, M. Chan, P. Ko, C. Hu

引用次数: 6

A 0.15 /spl mu/m KrF lithography for 1 Gb DRAM product using highly printable patterns and thin resist process 采用高可打印模式和薄抗蚀剂工艺的1gb DRAM产品的0.15 /spl mu/m KrF光刻技术

1998 Symposium on VLSI Technology Digest of Technical Papers (Cat. No.98CH36216) Pub Date : 1998-06-09 DOI: 10.1109/VLSIT.1998.689209

T. Ozaki, T. Azuma, M. Itoh, D. Kawamura, S. Tanaka, Y. Ishibashi, S. Shiratake, S. Kyoh, T. Kondoh, S. Inoue, K. Tsuchida, Y. Kohyama, Y. Onishi

引用次数: 3

High tolerance operation of 1T/2C FeRAMs for the variation of cell capacitors characteristics 1T/2C feram对电池电容特性变化的高容忍度操作

1998 Symposium on VLSI Technology Digest of Technical Papers (Cat. No.98CH36216) Pub Date : 1998-06-09 DOI: 10.1109/VLSIT.1998.689226

N. Tanabe, S. Kobayashi, T. Miwa, K. Amamuma, H. Mori, N. Inoue, T. Takeuchi, S. Saitoh, Y. Hayashi, J. Yamada, H. Koike, H. Hada, T. Hunio

引用次数: 8

Low resistance dual damascene process by new Al reflow using Nb liner 新型铌衬里铝回流低阻双腐蚀工艺

1998 Symposium on VLSI Technology Digest of Technical Papers (Cat. No.98CH36216) Pub Date : 1998-06-09 DOI: 10.1109/VLSIT.1998.689194

J. Wada, Y. Oikawa, T. Katata, N. Nakamura, M. B. Anand

引用次数: 9