J. Wada, Y. Oikawa, T. Katata, N. Nakamura, M. B. Anand
{"title":"Low resistance dual damascene process by new Al reflow using Nb liner","authors":"J. Wada, Y. Oikawa, T. Katata, N. Nakamura, M. B. Anand","doi":"10.1109/VLSIT.1998.689194","DOIUrl":null,"url":null,"abstract":"Summary form only given. This paper describes excellent Al filling characteristics and low resistance dual damascene interconnects obtained with a new Al reflow process using Nb liner. This novel process can fill vias of AR4 and can achieve 40-50% drop in resistance compared with current RIE-Al lines and reflow-Al lines with Ti liner. These properties are attributed to a slower reaction rate between Nb and Al. Excellent via electrical properties have been verified across 200 mm wafers using this process. This new process is a leading candidate for sub-0.25-0.15 um Al metallization.","PeriodicalId":402365,"journal":{"name":"1998 Symposium on VLSI Technology Digest of Technical Papers (Cat. No.98CH36216)","volume":"77 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1998-06-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"9","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"1998 Symposium on VLSI Technology Digest of Technical Papers (Cat. No.98CH36216)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/VLSIT.1998.689194","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 9
Abstract
Summary form only given. This paper describes excellent Al filling characteristics and low resistance dual damascene interconnects obtained with a new Al reflow process using Nb liner. This novel process can fill vias of AR4 and can achieve 40-50% drop in resistance compared with current RIE-Al lines and reflow-Al lines with Ti liner. These properties are attributed to a slower reaction rate between Nb and Al. Excellent via electrical properties have been verified across 200 mm wafers using this process. This new process is a leading candidate for sub-0.25-0.15 um Al metallization.