1998 Symposium on VLSI Technology Digest of Technical Papers (Cat. No.98CH36216)

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1998 Symposium on VLSI Technology Digest of Technical Papers (Cat. No.98CH36216) - 最新文献

A self-aligned STI process integration for low cost and highly reliable 1 Gbit flash memories

Pub Date : 1998-06-09 DOI: 10.1109/VLSIT.1998.689216 Y. Takeuchi, K. Shimizu, K. Narita, E. Kamiya, T. Yaegashi, K. Amemiya, S. Aritome

Highly scalable and fully logic compatible SRAM cell technology with metal damascene process and W local interconnect

Pub Date : 1998-06-09 DOI: 10.1109/VLSIT.1998.689200 M. Inohara, H. Oyamatsu, Y. Unno, Y. Fukaura, S. Goto, Y. Egi, M. Kinugawa

A high-performance sub-0.25 /spl mu/m CMOS technology with multiple thresholds and copper interconnects

Pub Date : 1998-06-09 DOI: 10.1109/VLSIT.1998.689182 L. Su, R. Schulz, J. Adkisson, K. Beyer, G. Biery, William J. Cote, Emmanuel F. Crabbe, Daniel C. Edelstein, J. Ellis-Monaghan, E. Eld, D. Foster, R. Gehres, R. Goldblatt, N. Greco, C. Guenther, John E. Heidenreich, J. Herman, D. Kiesling, L. Lin, S.-H. Lo, J. McKenna, C. Megivern, H. Ng, J. Oberschmidt, A. Ray, Norman J. Rohrer, K. Tallman, T. Wagner, B. Davari

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