Highly scalable and fully logic compatible SRAM cell technology with metal damascene process and W local interconnect

Abstract

For future SRAM cells, scalability with operation voltage reduction as well as device dimensions is very desirable. Moreover, higher compatibility with advanced logic process will become important more and more due to requirements from high performance SRAM-embedded LSIs such as RISC chips or multimedia LSIs. However, although a lot of candidates for the future SRAM cell have been reported, there have been few paper discussing systematically what kind of cell technology can be the main stream for future SRAM cells. In this paper, a SRAM technology with high scalability and excellent logic process compatibility has been proposed as a result of systematic consideration. In this technology, 6Tr. cell with small parasitic resistance is chosen for high cell stability under low operation voltage. W local interconnect (LI) is also implemented to realize smaller cell size with reduced bit-line capacitance. Moreover, cell layout as well as fabrication process is designed to be preferable for metal damascene process. With using damascene technology, W-LI can be fabricated by simple contact W-plug process simultaneously. As a result, highly scalable 6Tr. cell, which can be fabricated by an advanced logic process without any photo mask or process step increase, has been obtained. In order to demonstrate this cell technology, a 0.25 /spl mu/m SRAM cell with the cell size of 3.9 /spl mu/m/sup 2/ was fabricated and evaluated. Moreover, the scalability of this cell technology down to 0.15 /spl mu/m generation was confirmed by simulation.