A high-performance sub-0.25 /spl mu/m CMOS technology with multiple thresholds and copper interconnects

1998 Symposium on VLSI Technology Digest of Technical Papers (Cat. No.98CH36216) Pub Date : 1998-06-09 DOI:10.1109/VLSIT.1998.689182

L. Su, R. Schulz, J. Adkisson, K. Beyer, G. Biery, William J. Cote, Emmanuel F. Crabbe, Daniel C. Edelstein, J. Ellis-Monaghan, E. Eld, D. Foster, R. Gehres, R. Goldblatt, N. Greco, C. Guenther, John E. Heidenreich, J. Herman, D. Kiesling, L. Lin, S.-H. Lo, J. McKenna, C. Megivern, H. Ng, J. Oberschmidt, A. Ray, Norman J. Rohrer, K. Tallman, T. Wagner, B. Davari

引用次数: 32

Abstract

A sub-0.25 /spl mu/m technology in manufacturing that is targeted for high-performance CMOS applications is discussed. Aggressive groundrule scaling including SRAM cell size down to 5.4 /spl mu/m/sup 2/ is combined with multiple threshold voltage devices and the first technology in the industry to offer copper interconnects. These features result in minimum unloaded inverter delay of 12.7 ps and enable microprocessor frequencies above 480 MHz.

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一种高性能的低于0.25 /spl μ m的CMOS技术，具有多个阈值和铜互连

讨论了针对高性能CMOS应用的0.25 /spl mu/m以下制造技术。积极的接地规则缩放，包括SRAM单元尺寸降至5.4 /spl mu/m/sup 2/，结合多个阈值电压器件和业界首个提供铜互连的技术。这些特性导致最小卸载逆变器延迟12.7 ps，并使微处理器频率高于480 MHz。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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来源期刊

1998 Symposium on VLSI Technology Digest of Technical Papers (Cat. No.98CH36216)

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