Y. Takeuchi, K. Shimizu, K. Narita, E. Kamiya, T. Yaegashi, K. Amemiya, S. Aritome
{"title":"A self-aligned STI process integration for low cost and highly reliable 1 Gbit flash memories","authors":"Y. Takeuchi, K. Shimizu, K. Narita, E. Kamiya, T. Yaegashi, K. Amemiya, S. Aritome","doi":"10.1109/VLSIT.1998.689216","DOIUrl":null,"url":null,"abstract":"This paper describes a self-aligned Shallow Trench Isolation (STI) process integration to realize a low cost and high reliability 1 Gbit NAND flash memory. Peripheral low voltage CMOS transistors, high voltage transistors and small 5F/sup 2/ memory cells can be fabricated at the same time by using the self-aligned STI process. The advantages are as follows. (1) The number of process steps is reduced to 60% in comparison with a conventional process. (2) a high reliability of the gate oxide is realized even for high voltage transistors because the gate electrode does not overlap the trench corner. (3) A tight distribution of the threshold voltages (2.0 V) in a 2 Mbit memory cell array is achieved due to a good uniformity of the channel width in the self-aligned STI cells. Therefore this process integration combines a low cost with a high reliability for a manufacturable 1 Gbit flash memory.","PeriodicalId":402365,"journal":{"name":"1998 Symposium on VLSI Technology Digest of Technical Papers (Cat. No.98CH36216)","volume":"27 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1998-06-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"7","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"1998 Symposium on VLSI Technology Digest of Technical Papers (Cat. No.98CH36216)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/VLSIT.1998.689216","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 7
Abstract
This paper describes a self-aligned Shallow Trench Isolation (STI) process integration to realize a low cost and high reliability 1 Gbit NAND flash memory. Peripheral low voltage CMOS transistors, high voltage transistors and small 5F/sup 2/ memory cells can be fabricated at the same time by using the self-aligned STI process. The advantages are as follows. (1) The number of process steps is reduced to 60% in comparison with a conventional process. (2) a high reliability of the gate oxide is realized even for high voltage transistors because the gate electrode does not overlap the trench corner. (3) A tight distribution of the threshold voltages (2.0 V) in a 2 Mbit memory cell array is achieved due to a good uniformity of the channel width in the self-aligned STI cells. Therefore this process integration combines a low cost with a high reliability for a manufacturable 1 Gbit flash memory.