1T/2C feram对电池电容特性变化的高容忍度操作

1998 Symposium on VLSI Technology Digest of Technical Papers (Cat. No.98CH36216) Pub Date : 1998-06-09 DOI:10.1109/VLSIT.1998.689226

N. Tanabe, S. Kobayashi, T. Miwa, K. Amamuma, H. Mori, N. Inoue, T. Takeuchi, S. Saitoh, Y. Hayashi, J. Yamada, H. Koike, H. Hada, T. Hunio

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引用次数: 8

摘要

用8kbit单元阵列、感测放大器和其他外围电路演示了FeRAM测试芯片的工作，以确认1T/2C FeRAM的高容限。采用双层金属工艺成功制备了测试芯片。对于1T/2C FeRAM，在电池电容器特性退化和变化后，数据读取中放大的电压差为86 mV，足以运行，是传统1T/1C FeRAM的四倍。

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High tolerance operation of 1T/2C FeRAMs for the variation of cell capacitors characteristics

The operation of an FeRAM test chip is demonstrated with an 8 kbit cell array, sense amplifiers and other peripheral circuits for confirming the high tolerance of the 1T/2C FeRAM. The test chip is successfully fabricated by using a double layer metal process. The voltage difference to be amplified in data read for the 1T/2C FeRAM is 86 mV, which is large enough to operate, and four times larger than that for conventional 1T/1C FeRAM, after the cell capacitors characteristics are degraded and varied.

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来源期刊

1998 Symposium on VLSI Technology Digest of Technical Papers (Cat. No.98CH36216)

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