一种基于自对准通孔插头的多级互连气隙集成方案

1998 Symposium on VLSI Technology Digest of Technical Papers (Cat. No.98CH36216) Pub Date : 1998-06-09 DOI:10.1109/VLSIT.1998.689193

T. Ueda, E. Tamaoka, K. Yamashita, N. Aoi, S. Mayumi

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引用次数: 16

摘要

为了大幅度降低线间电容，提出了一种新型的多级互连工艺，实现了由传统SiO/sub /薄膜而非新型低k材料组成的气隙结构。得到有效相对介电常数为1.8。该工艺可以解决与气隙结构相关的重大问题，例如由于线和通孔水平之间的不对准而导致的通孔失效。

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A novel air gap integration scheme for multi-level interconnects using self-aligned via plugs

A novel multi-level interconnect process, realizing air gap structures composed of not new low k materials but conventional SiO/sub 2/ films, has been developed in order to drastically decrease the capacitance between lines. The effective relative dielectric constant of 1.8 is obtained. This process can solve the significant issues associated with air gap structure, such as the via failures due to misalignment between the line and via levels.

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来源期刊

1998 Symposium on VLSI Technology Digest of Technical Papers (Cat. No.98CH36216)

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