1998 Symposium on VLSI Technology Digest of Technical Papers (Cat. No.98CH36216)最新文献_第2页

Local mechanical stress induced defects for Ti and Co/Ti silicidation in sub-0.25 /spl mu/m MOS-technologies 在低于0.25 /spl mu/m的mos技术中，Ti和Co/Ti硅化的局部机械应力诱导缺陷

1998 Symposium on VLSI Technology Digest of Technical Papers (Cat. No.98CH36216) Pub Date : 1998-06-09 DOI: 10.1109/VLSIT.1998.689256

A. Steegen, K. Maex, I. De Wolf

引用次数: 6

Excellent process control technology for highly manufacturable and high performance 0.18 /spl mu/m CMOS LSIs 卓越的过程控制技术，可用于高度可制造和高性能的0.18 /spl mu/m CMOS lsi

1998 Symposium on VLSI Technology Digest of Technical Papers (Cat. No.98CH36216) Pub Date : 1998-06-09 DOI: 10.1109/VLSIT.1998.689234

T. Nakayama, T. Asamura, M. Kako, M. Murota, M. Matsumoto, Y. Washizu, K. Tomose, K. Kasai, Y. Okayama, K. Hashimoto, K. Ohuchi, K. Hattori, J. Shiozawa, H. Harakawa, F. Matsuoka, M. Kinugawa

引用次数: 0

Improved 0.12 /spl mu/m EB direct writing for Gbit DRAM fabrication 改进了用于gb DRAM制造的0.12 /spl mu/m EB直写

1998 Symposium on VLSI Technology Digest of Technical Papers (Cat. No.98CH36216) Pub Date : 1998-06-09 DOI: 10.1109/VLSIT.1998.689188

K. Nakajima, H. Yamashita, Y. Kojima, T. Tamura, Y. Yamada, K. Tokunaga, T. Ema, K. Kondoh, N. Onoda, H. Nozue

引用次数: 1

An evaluation of X-ray lithography using a 0.175 /spl mu/m (0.245 /spl mu/m/sup 2/ cell area) 1 Gb DRAM technology 采用0.175 /spl mu/m (0.245 /spl mu/m/sup 2/ cell面积)1gb DRAM技术的x射线光刻评价

1998 Symposium on VLSI Technology Digest of Technical Papers (Cat. No.98CH36216) Pub Date : 1998-06-09 DOI: 10.1109/VLSIT.1998.689208

R. Longo, S. Chaloux, A. Chen, A. Krasnoperova, S. Lee, G. Murphy, A. Thomas, C. Wasik, M. Weybright, G. Bronner

引用次数: 1

Gate-oxide degradation from source/drain (S/D) boron diffusion 源/漏(S/D)硼扩散的栅极-氧化物降解

1998 Symposium on VLSI Technology Digest of Technical Papers (Cat. No.98CH36216) Pub Date : 1998-06-09 DOI: 10.1109/VLSIT.1998.689255

K.P. Cheung, C. Chang, J. Colonell, W. Lai, C. Liu, R. Liu, C. Pai, C. Rafferty, H. Vaidya, J. Clemens

引用次数: 0

Limitation of post-metallization annealing due to hydrogen blocking effect of multilevel interconnect 多层互连的氢阻塞效应对金属化后退火的限制

1998 Symposium on VLSI Technology Digest of Technical Papers (Cat. No.98CH36216) Pub Date : 1998-06-09 DOI: 10.1109/VLSIT.1998.689249

S. Ito, K. Noguchi, T. Horiuchi, J. Clemens

引用次数: 0

A novel 6.4 /spl mu/m/sup 2/ full-CMOS SRAM cell with aspect ratio of 0.63 in a high-performance 0.25 /spl mu/m-generation CMOS technology 一种新颖的6.4 /spl mu/m/sup 2/全CMOS SRAM单元，采用高性能的0.25 /spl mu/m一代CMOS技术，纵横比为0.63

1998 Symposium on VLSI Technology Digest of Technical Papers (Cat. No.98CH36216) Pub Date : 1998-06-09 DOI: 10.1109/VLSIT.1998.689202

K.J. Kim, J. Youn, S. Kim, J. Kim, S.H. Hwang, K.T. Kim, Y. Shin

引用次数: 1

A new mode of hot carrier degradation in 0.18 /spl mu/m CMOS technologies 一种新的0.18 /spl μ m CMOS热载流子降解模式

1998 Symposium on VLSI Technology Digest of Technical Papers (Cat. No.98CH36216) Pub Date : 1998-06-09 DOI: 10.1109/VLSIT.1998.689246

C. Liu, E. J. Lloyd, C. Chang, K.P. Cheung, J. Colonell, W. Lai, R. Liu, C. Pai, H. Vaidya, J. Clemens

{"title":"A new mode of hot carrier degradation in 0.18 /spl mu/m CMOS technologies","authors":"C. Liu, E. J. Lloyd, C. Chang, K.P. Cheung, J. Colonell, W. Lai, R. Liu, C. Pai, H. Vaidya, J. Clemens","doi":"10.1109/VLSIT.1998.689246","DOIUrl":"https://doi.org/10.1109/VLSIT.1998.689246","url":null,"abstract":"In contrast to previous generations, we find that 0.18 /spl mu/m CMOS technologies exhibit completely different hot carrier degradation in both NMOS and PMOS devices. In addition to their smaller dimensions, the difference arises from high electric fields due to aggressive device designs for high current drives (I/sub on/). The high fields give rise to much more efficient impact-ionization and generate hot-holes which become dominant in the hot-carrier degradation, in contrast to the hot-electron injection in the previous generations. Therefore, it is essential to reduce hole trapping in thin gate oxides in order to improve the device lifetimes. We demonstrate that gate oxides grown on nitrogen ion-implanted (N I/I) Si substrates can significantly reduce hole trapping and the amount of degradation. Also, there exists a limit of the maximum power supply voltage (V/sub DD,max/) for reliable circuit operations. While aggressive device designs are commonly adopted to optimize I/sub on/, our results show that V/sub DD,max/ actually goes down almost linearly with the increase of I/sub on/ for the 0.18 /spl mu/m technologies.","PeriodicalId":402365,"journal":{"name":"1998 Symposium on VLSI Technology Digest of Technical Papers (Cat. No.98CH36216)","volume":"420 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-06-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123378684","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 1

Deuterium process of CMOS devices: new phenomena and dramatic improvement CMOS器件的氘制程:新现象和显著改进

1998 Symposium on VLSI Technology Digest of Technical Papers (Cat. No.98CH36216) Pub Date : 1998-06-09 DOI: 10.1109/VLSIT.1998.689248

Zhi Chen, Jinju Lee, J. Lyding, K. Hess

引用次数: 0

A shallow trench isolation with SiN guard-ring for sub-quarter micron CMOS technologies 用于亚四分之一微米CMOS技术的带有SiN保护环的浅沟槽隔离

1998 Symposium on VLSI Technology Digest of Technical Papers (Cat. No.98CH36216) Pub Date : 1998-06-09 DOI: 10.1109/VLSIT.1998.689260

T. Ogura, T. Yamamoto, Y. Saito, Y. Hayashi, T. Mogami

引用次数: 6