A shallow trench isolation with SiN guard-ring for sub-quarter micron CMOS technologies

Abstract

Shallow trench isolation (STI) technology is important to realize high-speed and high-packing-density CMOS-LSIs. A new SiN guard-ring on the upper edge of filled SiO/sub 2/ for steep-sidewall STI is proposed and evaluated to improve the reverse narrow channel effect and device reliability. Good isolation characteristics and sufficient improvement of the reverse narrow channel effect are achieved for STI with SiN guard-ring structure.