1998 Symposium on VLSI Technology Digest of Technical Papers (Cat. No.98CH36216)最新文献_第3页

CMOS RF modeling for GHz communication IC's GHz通信集成电路的CMOS射频建模

1998 Symposium on VLSI Technology Digest of Technical Papers (Cat. No.98CH36216) Pub Date : 1998-06-09 DOI: 10.1109/VLSIT.1998.689213

J. Ou, Xiaodong Jin, Ingrid Ma, C. Hu, Paul R. Gray

{"title":"CMOS RF modeling for GHz communication IC's","authors":"J. Ou, Xiaodong Jin, Ingrid Ma, C. Hu, Paul R. Gray","doi":"10.1109/VLSIT.1998.689213","DOIUrl":"https://doi.org/10.1109/VLSIT.1998.689213","url":null,"abstract":"With the advent of submicron technologies, GHz RF circuits can now be realized in a standard CMOS process. A major barrier to the realization of robust commercial CMOS RF components is the lack of adequate models which accurately predict MOSFET device behavior at high frequencies. The conventional microwave table-lookup-based approach requires a large database obtained from numerous device measurements and computationally intense simulations for accurate results. This method becomes prohibitively complex when used to simulate highly integrated CMOS communication systems; hence, a compact model, valid for a broad range of bias conditions and operating frequencies is desirable. BSIM3v3 has been widely accepted as a standard CMOS model for low frequency applications. Recent work has demonstrated the capability of modeling CMOS devices at high frequencies by utilizing a complicated substrate resistance network and extensive modification to the BSIM3v3 source code. This paper first describes a unified device model realized with a lumped resistance network suitable for simulations of both RF and baseband analog circuits; then verifies the accuracy of the model to measured data on both device and circuit levels.","PeriodicalId":402365,"journal":{"name":"1998 Symposium on VLSI Technology Digest of Technical Papers (Cat. No.98CH36216)","volume":"71 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-06-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125343267","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 114

Chemical mechanical polishing: the impact of a new technology on an industry 化学机械抛光:一项新技术对一个行业的影响

1998 Symposium on VLSI Technology Digest of Technical Papers (Cat. No.98CH36216) Pub Date : 1998-06-09 DOI: 10.1109/VLSIT.1998.689177

K. A. Perry

引用次数: 13

CVD photoresist processes for sub-0.18 design rules CVD光刻胶工艺的0.18以下设计规则

1998 Symposium on VLSI Technology Digest of Technical Papers (Cat. No.98CH36216) Pub Date : 1998-06-09 DOI: 10.1109/VLSIT.1998.689242

T. Weidman, D. Sugiarto, M. Nault, D. Mui, Z. Osborne, C. Lee, J. Yang

引用次数: 1

RF noise in 1.5 nm gate oxide MOSFETs and the evaluation of the NMOS LNA circuit integrated on a chip 1.5 nm栅极氧化mosfet中的射频噪声及片上集成NMOS LNA电路的评价

1998 Symposium on VLSI Technology Digest of Technical Papers (Cat. No.98CH36216) Pub Date : 1998-06-09 DOI: 10.1109/VLSIT.1998.689214

H. Momose, R. Fujimoto, S. Otaka, E. Morifuji, T. Ohguro, T. Yoshitomi, H. Kimijima, S. Nakamura, T. Morimoto, Y. Katsumata, H. Tanimoto, H. Iwai

引用次数: 18

A highly manufacturable 0.25 /spl mu/m multiple-Vt dual gate oxide CMOS process for logic/embedded IC foundry technology 用于逻辑/嵌入式IC铸造技术的高度可制造的0.25 /spl mu/m多vt双栅氧化CMOS工艺

1998 Symposium on VLSI Technology Digest of Technical Papers (Cat. No.98CH36216) Pub Date : 1998-06-09 DOI: 10.1109/VLSIT.1998.689236

M.H. Chang, J. Ting, J.S. Shy, L. Chen, C.W. Liu, J.Y. Wu, K. Pan, C. Hou, C. Tu, Y.H. Chen, S.L. Sue, S. Jang, S.C. Yang, C. Tsai, C. Chen, H. Tao, C. Tsai, H. Hsieh, Y.Y. Wang, R. Chang, K. Cheng, T. Chu, T. Yen, P. Wang, J. Weng, J.H. Hsu, Y. Ho, C. Ho, Y. Huang, R. Shiue, B. Liew, C. Yu, S.C. Sun, J. Sun

引用次数: 13

Stochastic net length distributions for global interconnects in a heterogeneous system-on-a-chip 异质片上系统中全局互连的随机网长分布

1998 Symposium on VLSI Technology Digest of Technical Papers (Cat. No.98CH36216) Pub Date : 1998-06-09 DOI: 10.1109/VLSIT.1998.689192

P. Zarkesh-Ha, J. Meindl

引用次数: 22

A new prediction method for oxide lifetime and its application to study dielectric breakdown mechanism 一种新的氧化物寿命预测方法及其在介质击穿机理研究中的应用

1998 Symposium on VLSI Technology Digest of Technical Papers (Cat. No.98CH36216) Pub Date : 1998-06-09 DOI: 10.1109/VLSIT.1998.689239

K. Okada, H. Kubo, A. Ishinaga, K. Yoneda

引用次数: 29

1.5 V operation sector-erasable flash memory with BIpolar Transistor Selected (BITS) P-channel cells 具有双极晶体管选择(BITS) p通道单元的1.5 V操作扇区可擦除闪存

1998 Symposium on VLSI Technology Digest of Technical Papers (Cat. No.98CH36216) Pub Date : 1998-06-09 DOI: 10.1109/VLSIT.1998.689180

T. Ohnakado, N. Ajika, H. Hayashi, H. Takada, K. Kobayashi, K. Sugahara, S. Satoh, H. Miyoshi

引用次数: 4

ARC for sub-0.18 /spl mu/m logic and gigabit DRAM frontend and backend processes ARC用于低于0.18 /spl mu/m的逻辑和千兆DRAM前端和后端进程

1998 Symposium on VLSI Technology Digest of Technical Papers (Cat. No.98CH36216) Pub Date : 1998-06-09 DOI: 10.1109/VLSIT.1998.689210

W.W. Lee, Qizhi He, A. Chatterjee, G. Xing, B. Brennan, A. Singh, E. Zielinski, M. Hanratty, Sunny Fang, D. Rogers, G. Dixit, D. Carter, J. D. Luttmer, B. Havermann, R. Chapman

引用次数: 1

Normally-off PLED (Planar Localised Electron Device) for non-volatile memory 用于非易失性存储器的正常关闭PLED(平面局部电子器件)

1998 Symposium on VLSI Technology Digest of Technical Papers (Cat. No.98CH36216) Pub Date : 1998-06-09 DOI: 10.1109/VLSIT.1998.689228

H. Mizuta, K. Nakazato, P. Piotrowicz, K. Itoh, T. Teshima, K. Yamaguchi, T. Shimada

引用次数: 10