A highly manufacturable 0.25 /spl mu/m multiple-Vt dual gate oxide CMOS process for logic/embedded IC foundry technology

Abstract

Summary form only given. A multiple-Vt high performance, high density and highly manufacturable 0.25 /spl mu/m CMOS technology with a shallow trench isolation process has been successfully developed. Five metal layers with oxide CMP planarization, etchback W plug for borderless contacts/vias, and fully stacked contact/vias were used. Dual gate oxide process (5 nm for 2.5 V core, and 7 nm for 3.3 V I/O or 13 nm for 5 V I/O) with low defect density, and low Vt (/spl sim/0.2 V) or native Vt (/spl sim/0 V) devices for low power and mixed-mode applications are all demonstrated in this technology.