1.5 V operation sector-erasable flash memory with BIpolar Transistor Selected (BITS) P-channel cells

1998 Symposium on VLSI Technology Digest of Technical Papers (Cat. No.98CH36216) Pub Date : 1998-06-09 DOI:10.1109/VLSIT.1998.689180

T. Ohnakado, N. Ajika, H. Hayashi, H. Takada, K. Kobayashi, K. Sugahara, S. Satoh, H. Miyoshi

引用次数: 4

Abstract

A novel BIpolar Transistor Selected (BITS) P-channel flash memory cell is proposed and a very low 1.5 V non-WL (word line)-boosting read and sector-erase operations are successfully achieved. Moveover, this cell technology not only maintains the advantages of the P-channel DINOR (DIvided bit line NOR) flash memory, but also realizes the amplification of cell current, which is favorable for fast access operation.

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具有双极晶体管选择(BITS) p通道单元的1.5 V操作扇区可擦除闪存

提出了一种新型的双极晶体管选择(BITS) p通道闪存单元，并成功实现了极低的1.5 V非wl(字线)增强读取和扇区擦除操作。此外，该小区技术既保持了p通道DINOR (DIvided bit line NOR)闪存的优点，又实现了小区电流的放大，有利于快速存取操作。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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来源期刊

1998 Symposium on VLSI Technology Digest of Technical Papers (Cat. No.98CH36216)

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