K.J. Kim, J. Youn, S. Kim, J. Kim, S.H. Hwang, K.T. Kim, Y. Shin
{"title":"A novel 6.4 /spl mu/m/sup 2/ full-CMOS SRAM cell with aspect ratio of 0.63 in a high-performance 0.25 /spl mu/m-generation CMOS technology","authors":"K.J. Kim, J. Youn, S. Kim, J. Kim, S.H. Hwang, K.T. Kim, Y. Shin","doi":"10.1109/VLSIT.1998.689202","DOIUrl":null,"url":null,"abstract":"Summary form only given. A unique 6.4 /spl mu/m/sup 2/ 6Tr. SRAM cell has been developed using an advanced CMOS technology implemented in 0.25 /spl mu/m design rule for high density and high speed applications. Very small aspect ratio of 0.63 has been achieved for the cell design. Special features in the layout are parallel active regions and orthogonal gate electrodes, all bar shape. Stable cell operation has been obtained at 0.5 V.","PeriodicalId":402365,"journal":{"name":"1998 Symposium on VLSI Technology Digest of Technical Papers (Cat. No.98CH36216)","volume":"95 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1998-06-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"1","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"1998 Symposium on VLSI Technology Digest of Technical Papers (Cat. No.98CH36216)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/VLSIT.1998.689202","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 1
Abstract
Summary form only given. A unique 6.4 /spl mu/m/sup 2/ 6Tr. SRAM cell has been developed using an advanced CMOS technology implemented in 0.25 /spl mu/m design rule for high density and high speed applications. Very small aspect ratio of 0.63 has been achieved for the cell design. Special features in the layout are parallel active regions and orthogonal gate electrodes, all bar shape. Stable cell operation has been obtained at 0.5 V.