T. Kachi, K. Shoji, H. Yamashita, T. Kisu, K. Torii, T. Kumihashi, Y. Fujisaki, N. Yokoyama
{"title":"一种可扩展的单晶体管/单电容存储单元结构,其特点是用于兆位feram的角度电容布局","authors":"T. Kachi, K. Shoji, H. Yamashita, T. Kisu, K. Torii, T. Kumihashi, Y. Fujisaki, N. Yokoyama","doi":"10.1109/VLSIT.1998.689227","DOIUrl":null,"url":null,"abstract":"A single-transistor/single-capacitor ferroelectric random access memory (FeRAM) cell having a cell size of 4.5 /spl mu/m/sup 2/ has been developed using 0.5-/spl mu/m technology. This cell features a stacked capacitor structure with a poly-Si plug and an angled-capacitor layout. This unique capacitor layout increases the alignment tolerance between the plate contact and the individual capacitor electrodes without increasing the cell area. O/sub 2/ annealing was applied after the plate-contact formation to restore the remanent polarization degradation. Favorable ferroelectric capacitor characteristics were observed when this cell was used in an experimental 4-Kbit memory-cell array.","PeriodicalId":402365,"journal":{"name":"1998 Symposium on VLSI Technology Digest of Technical Papers (Cat. No.98CH36216)","volume":"42 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1998-06-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"2","resultStr":"{\"title\":\"A scalable single-transistor/single-capacitor memory cell structure characterized by an angled-capacitor layout for megabit FeRAMs\",\"authors\":\"T. Kachi, K. Shoji, H. Yamashita, T. Kisu, K. Torii, T. Kumihashi, Y. Fujisaki, N. Yokoyama\",\"doi\":\"10.1109/VLSIT.1998.689227\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"A single-transistor/single-capacitor ferroelectric random access memory (FeRAM) cell having a cell size of 4.5 /spl mu/m/sup 2/ has been developed using 0.5-/spl mu/m technology. This cell features a stacked capacitor structure with a poly-Si plug and an angled-capacitor layout. This unique capacitor layout increases the alignment tolerance between the plate contact and the individual capacitor electrodes without increasing the cell area. O/sub 2/ annealing was applied after the plate-contact formation to restore the remanent polarization degradation. Favorable ferroelectric capacitor characteristics were observed when this cell was used in an experimental 4-Kbit memory-cell array.\",\"PeriodicalId\":402365,\"journal\":{\"name\":\"1998 Symposium on VLSI Technology Digest of Technical Papers (Cat. No.98CH36216)\",\"volume\":\"42 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1998-06-09\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"2\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"1998 Symposium on VLSI Technology Digest of Technical Papers (Cat. No.98CH36216)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/VLSIT.1998.689227\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"1998 Symposium on VLSI Technology Digest of Technical Papers (Cat. No.98CH36216)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/VLSIT.1998.689227","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
A scalable single-transistor/single-capacitor memory cell structure characterized by an angled-capacitor layout for megabit FeRAMs
A single-transistor/single-capacitor ferroelectric random access memory (FeRAM) cell having a cell size of 4.5 /spl mu/m/sup 2/ has been developed using 0.5-/spl mu/m technology. This cell features a stacked capacitor structure with a poly-Si plug and an angled-capacitor layout. This unique capacitor layout increases the alignment tolerance between the plate contact and the individual capacitor electrodes without increasing the cell area. O/sub 2/ annealing was applied after the plate-contact formation to restore the remanent polarization degradation. Favorable ferroelectric capacitor characteristics were observed when this cell was used in an experimental 4-Kbit memory-cell array.