Proceedings of 6th Electronics Packaging Technology Conference (EPTC 2004) (IEEE Cat. No.04EX971)最新文献_第7页

Engineering model for interfacial stresses of a tri-material assembly with different temperatures in the layers 具有不同层内温度的三材料组件界面应力的工程模型

Proceedings of 6th Electronics Packaging Technology Conference (EPTC 2004) (IEEE Cat. No.04EX971) Pub Date : 2004-12-08 DOI: 10.1109/EPTC.2004.1396665

D. Sujan, M. Murthy, K. N. Seetharamu, A.Y. Hassan

引用次数: 0

Design analysis of touch chip for enhanced package and board level reliability 提高封装和板级可靠性的触摸芯片设计分析

Proceedings of 6th Electronics Packaging Technology Conference (EPTC 2004) (IEEE Cat. No.04EX971) Pub Date : 2004-12-08 DOI: 10.1109/EPTC.2004.1396706

T. Y. Tee, H. Ng, H. Siegel, R. Bond, Z. Zhong

引用次数: 4

Structural optimization of fine pitch, large die flip chip package 细间距、大芯片倒装封装结构优化

Proceedings of 6th Electronics Packaging Technology Conference (EPTC 2004) (IEEE Cat. No.04EX971) Pub Date : 2004-12-08 DOI: 10.1109/EPTC.2004.1396586

A. Viswanath, W. Fang, T. Chai, N. Khan, S. Sampath

引用次数: 6

Pool boiling heat transfer enhancement by surface modification/micro-structures for electronics cooling: a review 电子冷却用表面改性/微结构强化池沸腾传热研究进展

Proceedings of 6th Electronics Packaging Technology Conference (EPTC 2004) (IEEE Cat. No.04EX971) Pub Date : 2004-12-08 DOI: 10.1109/EPTC.2004.1396618

N. Khan, D. Pinjala, K. Toh

引用次数: 39

Nanohardness study of CoSn/sub 2/ intermetallic layers formed between CO UBM and Sn flip-chip solder joints CO - UBM与Sn倒装焊点间形成的CoSn/sub - 2/金属间层的纳米硬度研究

Proceedings of 6th Electronics Packaging Technology Conference (EPTC 2004) (IEEE Cat. No.04EX971) Pub Date : 2004-12-08 DOI: 10.1109/EPTC.2004.1396630

P. Ratchev, R. Labie, E. Beyne

引用次数: 15

A numerical study of the effects of temperature, moisture and vapour pressure on delamination in a PQFP during solder reflow 焊料回流过程中温度、湿度和蒸汽压力对PQFP中分层影响的数值研究

Proceedings of 6th Electronics Packaging Technology Conference (EPTC 2004) (IEEE Cat. No.04EX971) Pub Date : 2004-12-08 DOI: 10.1109/EPTC.2004.1396585

Huang Guojun, A. Tay

{"title":"A numerical study of the effects of temperature, moisture and vapour pressure on delamination in a PQFP during solder reflow","authors":"Huang Guojun, A. Tay","doi":"10.1109/EPTC.2004.1396585","DOIUrl":"https://doi.org/10.1109/EPTC.2004.1396585","url":null,"abstract":"Delamination during solder reflow is a critical reliability problem for the plastic IC packages. The main objective of this paper is to investigate the effects of temperature, moisture diffusion and vapour pressure on the likelihood of delamination of the interface between the leadframe pad and the encapsulant. In this paper the entire thermal and moisture history of a plastic IC package is simulated from the start of level 1 moisture preconditioning (85/spl deg/C/85%RH for 168 hours) to subsequent exposure to a solder reflow process lasting about 5 minutes. The transient development of the strain energy release rate due to thermal stress only G/sub t/, hygrostress only G/sub h/, vapour pressure G/sub p/ and combined G/sub tot/ are computed and studied by using a new modified crack surface displacement extrapolation method (MCSDEM). Finite element models were constructed for a 160-leaded PQFP. The initial crack length was varied from 0.1mm to 3.5mm in order to study its effect. The results show that for small cracks, the effects of temperature and moisture are dominant while that of vapour pressure is insignificant. For moderate crack lengths, the effect of temperature is greatest. For large crack lengths, the effect of vapour pressure is dominant.","PeriodicalId":370907,"journal":{"name":"Proceedings of 6th Electronics Packaging Technology Conference (EPTC 2004) (IEEE Cat. No.04EX971)","volume":"62 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-12-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131745072","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 8

Bed of nails - 100 microns pitch wafer level interconnections process 钉床- 100微米间距晶圆级互连工艺

Proceedings of 6th Electronics Packaging Technology Conference (EPTC 2004) (IEEE Cat. No.04EX971) Pub Date : 2004-12-08 DOI: 10.1109/EPTC.2004.1396649

V. S. Rao, A. Tay, V. Kripesh, C. T. Lim, S. Yoon

{"title":"Bed of nails - 100 microns pitch wafer level interconnections process","authors":"V. S. Rao, A. Tay, V. Kripesh, C. T. Lim, S. Yoon","doi":"10.1109/EPTC.2004.1396649","DOIUrl":"https://doi.org/10.1109/EPTC.2004.1396649","url":null,"abstract":"The rapid advances in IC design and fabrication continue to challenge the electronic packaging technology, in terms of fine pitch, high performance, low cost and better reliability. In the near future, the demands for higher I/O count per integrated circuit (IC) chip increases as the shift towards the nano ICs with feature size less than 90nm. To meet the above requirements, the chip-to-substrate interconnection technologies with less than 100/spl mu/m pitch are required. Currently, the CTE mismatch between Si chip and substrate and assembly yield of such fine pitch interconnections serves as the biggest bottle neck issue. In this work a simple copper column based bed of nails-wafer level interconnects showing greater potentials in meeting some of these requirements for next-generation packaging is reported. The process development of fabricating the copper columns with various height and solder deposition on to the tip of the column is reported. This technology has been developed to meet fine pitch of 100 microns and high density interconnections. The development of a test chip demonstrator of 10 /spl times/ 10mm/sup 2/ with 3338 I/Os designed and fabricated for optimizing the process and the board level reliability test with out underfill performed under temperature cycling at range of -40/spl deg/C to 100/spl deg/C are also presented.","PeriodicalId":370907,"journal":{"name":"Proceedings of 6th Electronics Packaging Technology Conference (EPTC 2004) (IEEE Cat. No.04EX971)","volume":"21 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-12-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114655736","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 21

Design of double layer WLCSP using DOE with factorial analysis technology 利用DOE和析因分析技术设计双层WLCSP

Proceedings of 6th Electronics Packaging Technology Conference (EPTC 2004) (IEEE Cat. No.04EX971) Pub Date : 2004-12-08 DOI: 10.1109/EPTC.2004.1396713

Chang-Chun Lee, Shu-Ming Chang, K. Chiang

{"title":"Design of double layer WLCSP using DOE with factorial analysis technology","authors":"Chang-Chun Lee, Shu-Ming Chang, K. Chiang","doi":"10.1109/EPTC.2004.1396713","DOIUrl":"https://doi.org/10.1109/EPTC.2004.1396713","url":null,"abstract":"Newer, faster and smaller electronic packaging approaches with high I/O counts and more complex semiconductor devices are emerging steadily and rapidly. Wafer level chip scaling package (WLCSP) has a high potential for future electronic packaging. However, the solder joint reliability for a large chip size of about 100 mm/sup 2/ without underfill is remains a troubling issue that urgently requires a solution. To this end, a double-layer WLCSP (DL-WLCSP) with stress compliant layer and dummy solder joint is proposed in this research in order to enhance the solder joint fatigue life. To ensure the validity of the analysis methodology, a test vehicle of Rambus DRAM is implemented to demonstrate the applicability and reliability of the proposed DL-WLCSP. The results of the thermal cycling in the experimental test show good agreement with the simulated analysis. Furthermore, to investigate the reliability impact of the design parameters, including solder volume, the arrangement of the die-side and substrate-side pad diameter, pitch, compliant layer thickness, die thickness, and the printed circuit board (PCB) thickness, a design of experiment (DOE) with factorial analysis is adopted to obtain the sensitivity information of each parameter by the three-dimensional nonlinear finite element models (FEM). The statistics results of the analysis of variance reveal that the thickness of the stress compliant layer and the volume of the solder joint can effectively reduce the stress concentration phenomenon, which occurs around the outer-corner of the solder joint. In addition, the evident interaction between design parameters can also be obtained. The smaller thermal strains can be achieved through a better combination of design parameters of the geometry so as to provide the actual requirement of the physical information prior to manufacturing.","PeriodicalId":370907,"journal":{"name":"Proceedings of 6th Electronics Packaging Technology Conference (EPTC 2004) (IEEE Cat. No.04EX971)","volume":"36 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-12-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114623728","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 4

Modeling of solder joint failure due to PCB bending during drop impact 跌落冲击时PCB弯曲导致焊点失效的建模

Proceedings of 6th Electronics Packaging Technology Conference (EPTC 2004) (IEEE Cat. No.04EX971) Pub Date : 2004-12-08 DOI: 10.1109/EPTC.2004.1396694

Gu Jie, C. T. Lim, A. Tay

引用次数: 17

Time domain characterization of planar photonic crystal structures 平面光子晶体结构的时域表征

Proceedings of 6th Electronics Packaging Technology Conference (EPTC 2004) (IEEE Cat. No.04EX971) Pub Date : 2004-12-08 DOI: 10.1109/EPTC.2004.1396710

A. P. Popov

引用次数: 0