Proceedings of 6th Electronics Packaging Technology Conference (EPTC 2004) (IEEE Cat. No.04EX971)最新文献

{"title":"An effective method for calculation of corner stresses with applications to plastic IC packages","authors":"Zhou Wei, L. Meng, A. Tay","doi":"10.1109/TCAPT.2007.906736","DOIUrl":"https://doi.org/10.1109/TCAPT.2007.906736","url":null,"abstract":"Plastic IC packages are usually composite components made of multiple bonded materials with different mechanical and thermal properties. High stresses often occur around corners between different components within the packages where discontinuities of geometry or material properties are present. Delaminations usually initiate from these corners when packages undergo adverse thermal or moisture environments. Hence, in order to prevent delaminations from occurring and to improve package reliability performance, it is crucial to accurately and efficiently evaluate the stresses at corners within the package. However, with conventional finite element methods, it is always a challenge to give an accurate description of the stresses at the corners since these corners represent stress singularity points. An effective method is developed to precisely evaluate the stresses at the internal corners within the packages. A new variable-order singular boundary element is constructed with a built-in accurate description of the stresses at the corner. The boundary element method is adopted combined with the constructed variable-order singular element. This method is versatile for solving general corner problems involving wedges, two-material and three-material corners and interfacial cracks that are common in the IC packages. This method is verified by solving a bimaterial interface crack problem with known solution. Comparisons are made with other conventional methods, like displacement-based quarter-point singular elements and normal quadratic elements, on the calculation of interfacial stress intensity factors. Results show that the new method has significant advantages in giving more accurate results with much less computational resources needed. The new method is applied to a typical plastic IC package with multiple internal corners and interface cracks. The stress fields at these corners are calculated. The strain energy density distribution is also obtained from the results of stress fields. The possible failure sites and failure modes within the package are predicted and the results agree well with package evaluations done in the industry.","PeriodicalId":370907,"journal":{"name":"Proceedings of 6th Electronics Packaging Technology Conference (EPTC 2004) (IEEE Cat. No.04EX971)","volume":"27 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-05-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123467031","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Chip-package co-design of power distribution network for system-in-package applications","authors":"Gawon Kim, D. Kam, Daehyun Chung, Joungho Kim","doi":"10.1109/EPTC.2004.1396659","DOIUrl":"https://doi.org/10.1109/EPTC.2004.1396659","url":null,"abstract":"A new figure of merit for chip-package co-design of a power distribution network (PDN) is needed, not merely a voltage difference between power and ground at each hierarchy. In order to measure power supply noise as it is actually seen by the circuits in various locations on a chip, we need to chase the power/ground voltage with reference to a system ground. A PDN has two current paths; a series path and a shunt path. While the shunt path determines the voltage difference, the series path controls the power/ground voltage itself. Therefore, a balanced approach is strongly required rather than an excessive attention to the shunt path.","PeriodicalId":370907,"journal":{"name":"Proceedings of 6th Electronics Packaging Technology Conference (EPTC 2004) (IEEE Cat. No.04EX971)","volume":"13 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-12-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123114221","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"A new approach to low-temperature bonding for fine pitch chip-on-flex technology","authors":"Su-Tsai Lu","doi":"10.1109/EPTC.2004.1396646","DOIUrl":"https://doi.org/10.1109/EPTC.2004.1396646","url":null,"abstract":"In this work, plasma treatment, using argon and hydrogen mixed gas, was studied as pretreatment of Au electrode surface for chip-on-flex (COF) interconnection. Ion bombardment and chemical reactions of Ar/H/sub 2/ plasma with Au electrode surface were used for both surface activation and removal of surface contaminants. Contact angle measurement was used to evaluate the cleaning effect of the plasma treatment. Relationships of plasma treatment, bonding temperature, bonding pressure and peeling tests were also studied. Optimization of the plasma treatment time was achieved according to surface roughness on electrodes measured by atomic force microscopy (AFM) and verified by peeling tests. The criteria of peeling strength were also made by the failure mode of the bonding interfaces. After optimizing the plasma treatment time and bonding parameters, reliable joints with lower temperature and appropriate pressure were obtained compared with traditional COF bonding technology. After that, underfill was dispensed in the gap of COF bonding structure. After thermal shock reliability test (-55/spl deg/C/+125/spl deg/C, in liquid environment, 500 cycles), completive COF assemblies were used in LCD panel lighting-up test for inspecting the bonding quality. Cross section view on bonding interfaces were also observed by scanning electron microscopy (SEM). According to the results, it is possible to get reliable bonding quality and stable contact resistance of fine pitch COF interconnection at low temperature (150/spl deg/C) using surface activated method.","PeriodicalId":370907,"journal":{"name":"Proceedings of 6th Electronics Packaging Technology Conference (EPTC 2004) (IEEE Cat. No.04EX971)","volume":"105 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-12-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121804405","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Integrated antenna module for broadband wireless applications","authors":"A. Lu, K. M. Chua, L. L. Wai, S. Wong, J.J. Wang, Y.P. Zhang","doi":"10.1109/EPTC.2004.1396611","DOIUrl":"https://doi.org/10.1109/EPTC.2004.1396611","url":null,"abstract":"This paper describes a module based system integration using LTCC technology to realize a compact integrated antenna module. This approach enables the adoption of \"best-of-breed\" CMOS, SiGe and GaAs technologies for RF transceiver, power amplifier and antenna switch components. Key advantages of this module integration approach include integration of embedded passives, BGA or SMT assembly compatibility, co-design of RF components, wire-bond or flip-chip silicon interconnection and compact footprint. The integrated antenna module targeted for WLAN applications was realized using multi-layer LTCC fabrication technology. The module size is 17 /spl times/ 17 /spl times/ 2 mm/sup 3/, and can be seamlessly integrated with any planar antenna configuration. In addition to providing RF integration and improved system performance, this platform also enables improved thermal performance required for high power wireless applications whilst achieving a compact footprint for \"plug and play\" applications in portable mobile communication products.","PeriodicalId":370907,"journal":{"name":"Proceedings of 6th Electronics Packaging Technology Conference (EPTC 2004) (IEEE Cat. No.04EX971)","volume":"31 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-12-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121053003","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Finite element modeling of CSP package subjected to board level drop test","authors":"Y. Wang, F. Wang, T. Chai","doi":"10.1109/EPTC.2004.1396695","DOIUrl":"https://doi.org/10.1109/EPTC.2004.1396695","url":null,"abstract":"In the present study, finite element simulations are carried out to investigate the ball grid array (BGA) chip-scale package (CSP) subjected to board level drop impact loading. Firstly, a detail 3D model is built which includes the detailed pad geometry, exact shape of solder balls and local structures around the solder balls. The detail 3D model is used to investigate the critical failure location and components. Secondly, a corresponding simplified model is developed for the CSP package to simulate the global response and local effects of the system. Good agreements for the two models are demonstrated. Furthermore, a simulation methodology and strategy for CSP package is suggested by comparing and analyzing the simulation results for the two different models. The simplified model and simulation methodology are used for further investigations to reveal the critical chip location on a given PCB undergoing drop impact test.","PeriodicalId":370907,"journal":{"name":"Proceedings of 6th Electronics Packaging Technology Conference (EPTC 2004) (IEEE Cat. No.04EX971)","volume":"30 4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-12-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126089702","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Matte tin (Sn) plating: whisker growth study","authors":"A. Sriyarunya, J. Tondtan, D. Bansal","doi":"10.1109/EPTC.2004.1396619","DOIUrl":"https://doi.org/10.1109/EPTC.2004.1396619","url":null,"abstract":"In the industry's drive towards becoming lead-free (Pb-free) by July 1, 2006, as dictated by the WEEE Directive, several Pb-free terminal finishes have been proposed and evaluated. Some of them were rejected as soon as evaluations began. Others have been dropped along the way due to problems with either manufacturability or reliability. However, a few alternatives are becoming increasingly popular and seem to be the \"chosen ones\". SnAgCu alloys, for example, have emerged as the clear, choice for Pb-free solder. In contrast, there is no clear winner yet in the area of Pb-free plating alternatives. Electroplated matte tin (Sn) can be considered as a drop-in replacement for SnPb terminal finishes. However the tin whisker is often considered for pure tin plating. This paper presents the findings of a series of whisker growth studies performed on 100% matte Sn plating on Copper (Cu) leadframes. Studies were done on different package types, assembled at different locations at different times, with and without mitigation techniques and on samples at a component level (such as annealing etc.) and as mounted on PWBs. And also included study on plating additive and plating temperature effect on whisker growth on matte tin.. Since these studies started when no Pb-free or whisker definitions or standards were available, best known methods were employed in the studies. However, results from a new study done using NEMI's recommended Sn whisker test methods and failure criteria are also included.","PeriodicalId":370907,"journal":{"name":"Proceedings of 6th Electronics Packaging Technology Conference (EPTC 2004) (IEEE Cat. No.04EX971)","volume":"38 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-12-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125302903","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Thermal management and characterization of flip chip BGA packages","authors":"S. Krishnamoorthi, D.Y.R. Chong, A. Sun","doi":"10.1109/EPTC.2004.1396576","DOIUrl":"https://doi.org/10.1109/EPTC.2004.1396576","url":null,"abstract":"This paper presents the various types of thermally enhanced flip chip packages and its thermal characterization with thermal management options at package level. The conventional one-piece lid high performance flip chip BGA package (HP-fcBGA) has its strength in good thermal dissipation capability, however its board level solder joint reliability could be comprised due to the direct contact of the one-piece metal lid with the substrate. By encapsulating the flip chip with molding compound leaving the die top exposed, a planner top surface can be formed. And a flat lid can then be mounted on the planer mold/die top surface. In this way the direct interaction of metal lid with the substrate can be removed. The new extra performance flip chip BGA package (XP-fcBGA) is thus less rigid under thermal loading and solder joint reliability enhancement is expected. A third option of flip chip package XPs-fcBGA (with a dummy die between flip chip and metal lid as spacer) has been explored by UTAC for the solution of taller-than-flip-chip decoupling capacitors. This paper examines the thermal performance of XP-fcBGA and XPs-fcBGA packages versus the HP-fcBGA design. A series of experimental and computational studies were conducted to obtain the thermal resistance under JEDEC still and forced air (1m/s, 2m/s and 3m/s) environmental conditions. Experimental data of HP-fcBGA and XP-fcBGA recorded a thermal resistance thetasja 8.89deg.C/W and 8.86deg.C/W at zero airflow respectively, achieving good correlation with simulation results. Correlation within 10% range was also obtained for forced convection conditions of 1m/s, 2m/s and 3m/s airflow. Slight degradation in thermal performance of XPs-fcBGA was observed. Proper selection on the dummy die size is deemed necessary","PeriodicalId":370907,"journal":{"name":"Proceedings of 6th Electronics Packaging Technology Conference (EPTC 2004) (IEEE Cat. No.04EX971)","volume":"143 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-12-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122671282","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Correlation between ground bounce and radiated emission","authors":"K. See, O. Manish, Z.H. Liu, K. L. Kyaw","doi":"10.1109/EPTC.2004.1396686","DOIUrl":"https://doi.org/10.1109/EPTC.2004.1396686","url":null,"abstract":"High-speed PCB designers are facing challenges while designing electronic systems to meet the international electromagnetic compatibility (EMC) regulatory requirements. A PCB that carries high-speed circuit can radiate significant amount of electromagnetic emissions if no attention is paid on the layout of the circuit. With a practical case study, This work demonstrates that there is a strong correlation between ground bounce and radiated emissions of a high-speed circuit.","PeriodicalId":370907,"journal":{"name":"Proceedings of 6th Electronics Packaging Technology Conference (EPTC 2004) (IEEE Cat. No.04EX971)","volume":"36 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-12-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122685097","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Pressure and depth dependence of sidewall roughness of polymer optical waveguides during reactive ion etching","authors":"S. Pani, C. Wong, C. Premachandran, M. Iyer, P. Ramana, V. Lim, N. Ranganathan","doi":"10.1109/EPTC.2004.1396638","DOIUrl":"https://doi.org/10.1109/EPTC.2004.1396638","url":null,"abstract":"Sidewall roughness (SWR) of fluorinated polyether waveguides fabricated using reactive ion etching in pure oxygen gas was directly measured using atomic force microscope (AFM). We confirmed that SWR is not the replicate of line edge roughness (LER) of the waveguides. We also confirmed the pressure dependence of SWR for shallow structures and discovered an additional etch depth dependence for deeper structures which counteracts the pressure dependence. Lower O/sub 2/ pressure etching produces SWR which increases with depth while higher O/sub 2/ pressure etching produces declining SWR with depth. The depth dependence at lower pressure is explained by the change in the arrival dynamics of etchant ions in a mechanism involving both shadowing and first order reemission effects.","PeriodicalId":370907,"journal":{"name":"Proceedings of 6th Electronics Packaging Technology Conference (EPTC 2004) (IEEE Cat. No.04EX971)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-12-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122730004","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Transient simulation of solder joint fracturing under impact test","authors":"Chang-Lin Yen, Y. Lai","doi":"10.1109/EPTC.2004.1396696","DOIUrl":"https://doi.org/10.1109/EPTC.2004.1396696","url":null,"abstract":"In this paper, transient deformation and fracturing of solder joints subjected to the impact load are investigated numerically. The three-dimensional finite element analysis applies the explicit time integration scheme and incorporates as well contact, fracturing and fragmentation mechanisms to predict the transient response and the failure mode of the solder joint subjected to an impact load.","PeriodicalId":370907,"journal":{"name":"Proceedings of 6th Electronics Packaging Technology Conference (EPTC 2004) (IEEE Cat. No.04EX971)","volume":"58 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-12-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128318707","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}