Finite element modeling of CSP package subjected to board level drop test

Abstract

In the present study, finite element simulations are carried out to investigate the ball grid array (BGA) chip-scale package (CSP) subjected to board level drop impact loading. Firstly, a detail 3D model is built which includes the detailed pad geometry, exact shape of solder balls and local structures around the solder balls. The detail 3D model is used to investigate the critical failure location and components. Secondly, a corresponding simplified model is developed for the CSP package to simulate the global response and local effects of the system. Good agreements for the two models are demonstrated. Furthermore, a simulation methodology and strategy for CSP package is suggested by comparing and analyzing the simulation results for the two different models. The simplified model and simulation methodology are used for further investigations to reveal the critical chip location on a given PCB undergoing drop impact test.