Proceedings of 6th Electronics Packaging Technology Conference (EPTC 2004) (IEEE Cat. No.04EX971)最新文献_第2页

Process development of a flip chip in package with anisotropic conductive film (ACF) for lead-free soldering 各向异性导电膜(ACF)封装倒装芯片无铅焊接工艺开发

Proceedings of 6th Electronics Packaging Technology Conference (EPTC 2004) (IEEE Cat. No.04EX971) Pub Date : 2004-12-08 DOI: 10.1109/EPTC.2004.1396650

S. Lim Pei Siang, T. Min, C. Lee

{"title":"Process development of a flip chip in package with anisotropic conductive film (ACF) for lead-free soldering","authors":"S. Lim Pei Siang, T. Min, C. Lee","doi":"10.1109/EPTC.2004.1396650","DOIUrl":"https://doi.org/10.1109/EPTC.2004.1396650","url":null,"abstract":"In our previous work, we have established a baseline anisotropic conductive adhesive (ACA) assembly process with positive temperature cycling and temperature humidity reliability results. With the experience gained, further work was carried out to assess the compatibility of anisotropic conductive film (ACF) technology for high I/O applications in lead-free soldering conditions. Here, we report the assembly process development of a 13mm /spl times/ 13mm flip chip BGA package using ACF to meet the stringent reflow temperature of 260/spl deg/C, required for lead-free soldering. The effects of bond pressure distribution and alignment accuracy was found to be more critical in this 8mm /spl times/ 8mm test die and 800 flip chip bumps. A three-factor design of experiment (DOE) was carried out to investigate the effects of assembly parameters such as bonding pressure, temperature and time on moisture sensitivity level (MSL) performance reflowed at 260/spl deg/C. Results showed that higher bond force is undesirable and contributes to delamination at critical interfaces. With process optimization, the flip chip BGA with large die and high I/O was able to meet lead-free soldering requirement.","PeriodicalId":370907,"journal":{"name":"Proceedings of 6th Electronics Packaging Technology Conference (EPTC 2004) (IEEE Cat. No.04EX971)","volume":"24 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-12-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124663859","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 9

150 /spl mu/m pitch flipchip packaging with Pb-free solder and Cu/low-k interconnects 150 /spl μ /m间距倒装芯片封装，无铅焊料和Cu/低k互连

Proceedings of 6th Electronics Packaging Technology Conference (EPTC 2004) (IEEE Cat. No.04EX971) Pub Date : 2004-12-08 DOI: 10.1109/EPTC.2004.1396590

S. Yoon, V. Kripesh, L. Yu, M. Iyer

引用次数: 3

To simulate the formation of TSSOP solder joint with SAC solder and assess on the effects of the stencil design and the misalignment on the joint shape 模拟TSSOP焊点与SAC焊点的形成过程，并评估焊条设计和对中偏差对焊点形状的影响

Proceedings of 6th Electronics Packaging Technology Conference (EPTC 2004) (IEEE Cat. No.04EX971) Pub Date : 2004-12-08 DOI: 10.1109/EPTC.2004.1396625

X.J. Zhao, J. Caers

{"title":"To simulate the formation of TSSOP solder joint with SAC solder and assess on the effects of the stencil design and the misalignment on the joint shape","authors":"X.J. Zhao, J. Caers","doi":"10.1109/EPTC.2004.1396625","DOIUrl":"https://doi.org/10.1109/EPTC.2004.1396625","url":null,"abstract":"Robustness of solder interconnection highly depends on solder joint geometry which is largely governed by the surface tension of solder paste, the wettability of the solder paste on the component finish and on the solder land, and the geometry/dimension of the solder land on the substrate and the component lead. With the mandatory trends to launch Pb-free in most electronics application and the increasing interconnect miniaturisation in electronics packaging, the effect of the surface tension of liquid solder alloy, the design parameters, e.g. solder volume, and the process parameters, e.g. the misalignment, on the solder joint geometry, and the criteria for acceptable design/process parameters for a reliable interconnection are more and more attractive in actual industry manufacturing. In this study, with a typical Philips component/package TSSOP (thin shrink small outline package) as a example, a developed numerical model to predict the equilibrium shape of a liquid was applied in Surface Evolver, and the formation of the solder joint between the TSSOP package to the Cu pad on the PCB during reflow is simulated. With the model, the geometries of the TSSOP solder joint with eutectic Sn-Ag-Cu (SAC) solder and traditional eutectic SnPb solder were predicted and compared, and the effect of the different stencil design and the misalignment of the lead to the pad on the solder shapes is predicted, and the predicted result showed a good match with the result from the lab test. Finally, a criteria/margin is suggested to define these design/process parameters for the TSSOP package.","PeriodicalId":370907,"journal":{"name":"Proceedings of 6th Electronics Packaging Technology Conference (EPTC 2004) (IEEE Cat. No.04EX971)","volume":"58 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-12-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121494601","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 3

Impact of substrate finish on Sn/Ag/Cu alloy solder joint 衬底光洁度对Sn/Ag/Cu合金焊点的影响

Proceedings of 6th Electronics Packaging Technology Conference (EPTC 2004) (IEEE Cat. No.04EX971) Pub Date : 2004-12-08 DOI: 10.1109/EPTC.2004.1396629

A. Anand, Y. Mui, J. Weidier, N. Diaz

{"title":"Impact of substrate finish on Sn/Ag/Cu alloy solder joint","authors":"A. Anand, Y. Mui, J. Weidier, N. Diaz","doi":"10.1109/EPTC.2004.1396629","DOIUrl":"https://doi.org/10.1109/EPTC.2004.1396629","url":null,"abstract":"In recent years, implementation of lead-free solder in the electronic industry is gaining momentum. Lower processing temperature and reliability of a Sn/Ag/Cu alloy has made it a viable alternative and the industry is aligning towards this alloy. This work investigates impact of substrate finish on Sn/Ag/Cu alloy for ball grid array packages. The scope of This work includes study of lead-free alloy Sn/Ag/Cu, Sn/Ag & Sn/Cu, its interaction with substrate plating finish, intermetallic at substrate-ball interface, shear force and failure mode. The type of substrate used in this study is buildup substrate with electroless nickel gold finish and laminate substrate with electrolytic nickel gold finish. Experimental results show that copper containing alloys exhibited failure mode at IMC/nickel interface, when shear test was performed on the units reflowed three times at 260deg. The conclusion from the above study is, Sn/Ag/Cu solder alloy used in ball grid array can result in fracture at IMC /electrolytic nickel interface. Impact force from testers or drop test can result in such brittle fracture between IMC and nickel. Increasing the copper percentage in Sn/Ag/Cu alloy can increase the chance of this brittle fracture between the IMC and electrolytic nickel interface.","PeriodicalId":370907,"journal":{"name":"Proceedings of 6th Electronics Packaging Technology Conference (EPTC 2004) (IEEE Cat. No.04EX971)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-12-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127749831","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 9

Modelling and application of silicon microphone systems 硅传声器系统的建模与应用

Proceedings of 6th Electronics Packaging Technology Conference (EPTC 2004) (IEEE Cat. No.04EX971) Pub Date : 2004-12-08 DOI: 10.1109/EPTC.2004.1396600

H-T. Mammen, U. Sturmer, M. Koch, H. Kohne, K. Becker, W. John, H. Reichl

引用次数: 0

Design for electrical performance of wideband multilayer LTCC microstrip-to-stripline transition 宽带多层LTCC微带到带线转换的电气性能设计

Proceedings of 6th Electronics Packaging Technology Conference (EPTC 2004) (IEEE Cat. No.04EX971) Pub Date : 2004-12-08 DOI: 10.1109/EPTC.2004.1396661

Huei-Han Jhuang, Tian-Wei Huang

引用次数: 13

Numerical modeling of annular flow in microchannel 微通道内环形流动的数值模拟

Proceedings of 6th Electronics Packaging Technology Conference (EPTC 2004) (IEEE Cat. No.04EX971) Pub Date : 2004-12-08 DOI: 10.1109/EPTC.2004.1396673

Y. Yap, K. Toh, T. Wong, J. Chai

引用次数: 1

Low temperature Si-to-Si wafer bonding with sol-gel coating as intermediate layer 以溶胶-凝胶涂层为中间层的低温硅对硅晶片键合

Proceedings of 6th Electronics Packaging Technology Conference (EPTC 2004) (IEEE Cat. No.04EX971) Pub Date : 2004-12-08 DOI: 10.1109/EPTC.2004.1396601

J. Wei, S. Deng, C. Tan, C.K. Wong

引用次数: 2

Reliability improvement in low loop nailhead wirebonding for long Au wire in a high stress encapsulant material 高应力封装材料中长金线低环钉头焊接可靠性的提高

Proceedings of 6th Electronics Packaging Technology Conference (EPTC 2004) (IEEE Cat. No.04EX971) Pub Date : 2004-12-08 DOI: 10.1109/EPTC.2004.1396699

A. K. Yahya, L. Ling, Toh Ling Hoe

{"title":"Reliability improvement in low loop nailhead wirebonding for long Au wire in a high stress encapsulant material","authors":"A. K. Yahya, L. Ling, Toh Ling Hoe","doi":"10.1109/EPTC.2004.1396699","DOIUrl":"https://doi.org/10.1109/EPTC.2004.1396699","url":null,"abstract":"There has been many innovations and technological advancement in the gold wire bond for semiconductor applications in recent years. The development of several categories and types of gold wire was triggered by the various needs of the end users in this industry. The right selection of wire for low loop bonding of long wire bond is critical to meet the final product quality and reliability requirement. Coupled with the product needs for a special but high CTE encapsulation material, the resultant stresses on the wire in a complete package and at elevated condition has dampened the wire bond reliability performance. In this detail study, the influence of the wire properties, the wire bond parameters, and the wire loop profile were analyzed and reviewed. To achieve the desired low loop wire height for such long wire length, two wire types with low HAZ, high tensile strength, suitable hardness and elongation properties were choosen for the initial evaluation. The result revealed that the wire with an assumed better control in dopant and drawing process has produced smaller process variation sigma in almost all of the performed quality tests. The next step was to study the influence of the HAZ length and the loop bending point on the product reliability. In this study, the HAZ length was maintained and the loop bending points were varied. In addition, a suitable wire bond capilary movement was established to achieve the desired loop height. The reliability screening test revealed that the units with low bending point within the HAZ length failed at early readouts. The separation was due to the grain boundary stress in the larger grain size at the beginning of the HAZ length. In conclusion, the reliability of long and low loop Au wire in high stress encapsulant material can be achieved by the proper selection of the wire type, wire bonding parameters, and loop profile with relation to the HAZ length.","PeriodicalId":370907,"journal":{"name":"Proceedings of 6th Electronics Packaging Technology Conference (EPTC 2004) (IEEE Cat. No.04EX971)","volume":"118 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-12-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117106725","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 2

Fractal analysis of Sn-Ag, Sn-Ag-Cu, Sn-Ag-Bi interfacial morphology in flipchip packaging applications 倒装封装中Sn-Ag、Sn-Ag- cu、Sn-Ag- bi界面形貌的分形分析

Proceedings of 6th Electronics Packaging Technology Conference (EPTC 2004) (IEEE Cat. No.04EX971) Pub Date : 2004-12-08 DOI: 10.1109/EPTC.2004.1396682

R. Jayaganthan, K. Mohankumar, A. Tay, V. Kripesh

引用次数: 0