150 /spl mu/m pitch flipchip packaging with Pb-free solder and Cu/low-k interconnects

Proceedings of 6th Electronics Packaging Technology Conference (EPTC 2004) (IEEE Cat. No.04EX971) Pub Date : 2004-12-08 DOI:10.1109/EPTC.2004.1396590

S. Yoon, V. Kripesh, L. Yu, M. Iyer

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引用次数: 3

Abstract

Low-k test vehicles with four Cu layers are fabricated using Cu dual damascene process. Polymer encapsulation and metal redistribution is applied using wafer integration technology to minimize the stress from the solder bump pad to low-k ILD (interlayer dielectric). Two different interconnections were studied; i) Pb-free solder bump and ii) copper column. Ti/NiV/Cu/Au UBM is deposited on the Cu/low-k wafers and Sn-4.0Ag-0.5Cu Pb-free solder are bumped for solder interconnection. For copper column interconnection, thick PR process is developed and optimized for electro Cu plating and solder is deposited on the top of Cu post. Bump shear test is carried out to evaluate the bump bonding and analyzed the failure. In order to investigate UBM and solder joint reliability, multiple reflows were carried out. Microstructure observation and failure analysis were performed and observed with optical and electron microscopy. The paper will also present the reliability and failure analysis studies carried out in characterizing the UBM structures.

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150 /spl μ /m间距倒装芯片封装，无铅焊料和Cu/低k互连

采用Cu双damascend工艺制备了四层Cu低钾试验车。聚合物封装和金属再分配采用晶圆集成技术，以尽量减少从焊料凹凸垫到低k ILD(层间介电)的应力。研究了两种不同的互连;i)无铅焊点和ii)铜柱。Ti/NiV/Cu/Au UBM沉积在Cu/low-k晶片上，并碰撞Sn-4.0Ag-0.5Cu - pb无焊料进行焊料互连。对于铜柱互连，开发并优化了电镀铜的厚PR工艺，并在铜柱顶部沉积焊料。通过碰撞剪切试验对碰撞粘结进行了评价，并对碰撞粘结破坏进行了分析。为了研究UBM和焊点的可靠性，进行了多次回流试验。进行了显微组织观察和失效分析，并用光学显微镜和电子显微镜进行了观察。本文还将介绍在表征UBM结构时进行的可靠性和失效分析研究。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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Proceedings of 6th Electronics Packaging Technology Conference (EPTC 2004) (IEEE Cat. No.04EX971)

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