面向系统级封装应用的配电网芯片封装协同设计

Gawon Kim, D. Kam, Daehyun Chung, Joungho Kim
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引用次数: 3

摘要

对于配电网(PDN)的芯片封装协同设计,需要一种新的性能指标,而不仅仅是各层电源和地之间的电压差。为了测量电源噪声,因为它实际上是由芯片上不同位置的电路所看到的,我们需要根据系统地来跟踪电源/地电压。PDN有两条电流路径;一个串联路径和一个并联路径。当并联路径决定电压差时,串联路径控制电源/地电压本身。因此,一个平衡的方法是强烈需要的,而不是过分关注分流路径。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
Chip-package co-design of power distribution network for system-in-package applications
A new figure of merit for chip-package co-design of a power distribution network (PDN) is needed, not merely a voltage difference between power and ground at each hierarchy. In order to measure power supply noise as it is actually seen by the circuits in various locations on a chip, we need to chase the power/ground voltage with reference to a system ground. A PDN has two current paths; a series path and a shunt path. While the shunt path determines the voltage difference, the series path controls the power/ground voltage itself. Therefore, a balanced approach is strongly required rather than an excessive attention to the shunt path.
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