Proceedings of 6th Electronics Packaging Technology Conference (EPTC 2004) (IEEE Cat. No.04EX971)最新文献_第6页

Improved monitoring of ultrasonic wire bonding via input electrical impedance 通过输入电阻抗改进超声焊线的监测

Proceedings of 6th Electronics Packaging Technology Conference (EPTC 2004) (IEEE Cat. No.04EX971) Pub Date : 2004-12-08 DOI: 10.1109/EPTC.2004.1396634

Dong Zhang, S. Ling, Sung Yi, Say Wee Foo

{"title":"Improved monitoring of ultrasonic wire bonding via input electrical impedance","authors":"Dong Zhang, S. Ling, Sung Yi, Say Wee Foo","doi":"10.1109/EPTC.2004.1396634","DOIUrl":"https://doi.org/10.1109/EPTC.2004.1396634","url":null,"abstract":"The technology of using input electrical impedance to monitor a process of ultrasonic wire bonding has existed for a few decades. From literature it is seen that the waveforms of \"impedance\" in these methods were detected only approximately and much information was missing. In this paper, the method of detecting electrical impedance is improved so that the true waveforms of both the real and imaginary part of the input impedance of a wire bonder are detected and used to monitor bond quality and machine operation condition in-situ and real-time. In order to automate the monitoring, 25 features of the waveforms were selected and fed into a 3 layer back propagation artificial neural network which provides condition indicators after proper training. Since the input impedance characterizes the behavior of a dynamic system completely, once accurate measurement is made, it allows accurate prediction of bond strength. Comparison with results obtained from off-line standard shear tests well demonstrates this capability. When trained to identify operation conditions, the proposed system also identifies the drifting of operation parameters quite accurately","PeriodicalId":370907,"journal":{"name":"Proceedings of 6th Electronics Packaging Technology Conference (EPTC 2004) (IEEE Cat. No.04EX971)","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-12-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130766707","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Modelling of free air ball for copper wire bonding 铜线粘接自由空气球的建模

Proceedings of 6th Electronics Packaging Technology Conference (EPTC 2004) (IEEE Cat. No.04EX971) Pub Date : 2004-12-08 DOI: 10.1109/EPTC.2004.1396700

J. Tan, B. Toh, H. Ho

{"title":"Modelling of free air ball for copper wire bonding","authors":"J. Tan, B. Toh, H. Ho","doi":"10.1109/EPTC.2004.1396700","DOIUrl":"https://doi.org/10.1109/EPTC.2004.1396700","url":null,"abstract":"Copper wire ball bonding has gained considerable attention due to its economic advantage, strong resistance to sweeping and superior electrical performance. In order to have a good first bond, consistent free air-ball formation for copper bonding are even more crucial than they are in the gold wire process. To create a free air ball (FAB), the wire bonder uses an electronic flame-off (EFO) unit, where high voltage is connected. During operation, the EFO gap is breached by a high current, creating a high voltage spark, which melt the tail of the copper wire in a glow discharge to form a spherical ball. Unlike gold wire, copper wire oxidizes readily. Hence, during the formation of the FAB, the copper wire must be enclosed in an inert gas environment in order to prevent oxidisation of the FAB. In this study, an empirical methodology was developed to model a consistent FAB for copper wire diameters ranging from 0.8mil to 2.0mil. Cherry pit bonds were created to study the FAB. Numerous tests were run on an automatic ball bonder in which current and time were varied and the resulting ball size measured. These data points were then used as inputs for the empirical model. This methodology uses the EFO current and time as measurable energy inputs and the FAB size as the measurable energy output. It is simple to use and has the advantage of avoiding complex computation of phenomena analysis, which involves the phase change during FAB melting and formation. It is also able to predict copper wire FAB to provide consistent FAB size.","PeriodicalId":370907,"journal":{"name":"Proceedings of 6th Electronics Packaging Technology Conference (EPTC 2004) (IEEE Cat. No.04EX971)","volume":"8 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-12-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134069617","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 28

Ultra fine-pitch wafer level packaging with reworkable composite nano-interconnects 超细间距晶圆级封装与可修复的复合纳米互连

Proceedings of 6th Electronics Packaging Technology Conference (EPTC 2004) (IEEE Cat. No.04EX971) Pub Date : 2004-12-08 DOI: 10.1109/EPTC.2004.1396591

A. Aggarwal, P. Markondeya Raj, M. Sacks, A. Tay, R. Tummala

{"title":"Ultra fine-pitch wafer level packaging with reworkable composite nano-interconnects","authors":"A. Aggarwal, P. Markondeya Raj, M. Sacks, A. Tay, R. Tummala","doi":"10.1109/EPTC.2004.1396591","DOIUrl":"https://doi.org/10.1109/EPTC.2004.1396591","url":null,"abstract":"The decrease in feature sizes of micro-electronic devices has underlined the need for higher number of I/O's in order to increase its functionality. This has spurred a great interest in developing electronic packages with fine and ultra fine pitches (20-100 microns). Most of the compliant interconnects that are currently being developed have inductance and resistance higher than desirable. This work presents a novel low-temperature fabrication process that combines polymer structures with electroless copper plating to create low stress MEMS structures for extremely fine pitch wafer level packages. Finite element analysis of these structures shows tremendous reduction in the stresses at the interfaces and superior reliability as IC-package nano interconnects. Low CTE polyimide structures with ultra-low stress, high toughness and strength were fabricated using plasma etching. This dry etching process was tuned to yield a wall angle above 80 degrees. The etching process also leads to roughened sidewalls for selective electroless copper plating on the sidewalls of polymer structures. Metal-coated polymer structures from MEMS fabrication techniques can provide low-cost high-performance solutions for wafer-level-packaging. This work also describes a material solution synthesis route to develop reworkable nano-dimensional interfaces for IC-package bonding. Reworkability is addressed by a thin (200 nm) interface of lead-free high-strength solders using selective electroless plating. Lead-free alloy films were deposited from aqueous plating solutions consisting of suitable metal salts and reducing agents at 45/spl deg/C. The lead-free solder composition was controlled by altering the plating bath formulation and was characterized using SEM, XRD and XPS. Solder film formed from the above approach was demonstrated to bond the metal-coated polymer interconnects with the copper pads on the substrate.","PeriodicalId":370907,"journal":{"name":"Proceedings of 6th Electronics Packaging Technology Conference (EPTC 2004) (IEEE Cat. No.04EX971)","volume":"11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-12-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134074694","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 8

Fully cure-dependent polymer modeling and application to QFN-packages warpage 完全依赖于固化的聚合物建模及其在qfn封装翘曲中的应用

Proceedings of 6th Electronics Packaging Technology Conference (EPTC 2004) (IEEE Cat. No.04EX971) Pub Date : 2004-12-08 DOI: 10.1109/EPTC.2004.1396582

D.G. Yang, L. Ernst, K. Jansen, C. van't Hof, G.Q. Zhang, W. V. van Driel, H. Bressers

引用次数: 5

Hygro-thermo-mechanical modeling of mixed flip-chip and wire bond stacked die BGA module with molded underfill 混合倒装芯片和线键堆叠模BGA模组的湿热力学建模

Proceedings of 6th Electronics Packaging Technology Conference (EPTC 2004) (IEEE Cat. No.04EX971) Pub Date : 2004-12-08 DOI: 10.1109/EPTC.2004.1396684

Xueren Zhang, T. Y. Tee, H. Ng, J. Teysseyre, S. Loo, S. Mhaisalkar, F. Ng, C. T. Lim, Xinyu Du, E. Bool, Wenhui Zhu, S. Chew

{"title":"Hygro-thermo-mechanical modeling of mixed flip-chip and wire bond stacked die BGA module with molded underfill","authors":"Xueren Zhang, T. Y. Tee, H. Ng, J. Teysseyre, S. Loo, S. Mhaisalkar, F. Ng, C. T. Lim, Xinyu Du, E. Bool, Wenhui Zhu, S. Chew","doi":"10.1109/EPTC.2004.1396684","DOIUrl":"https://doi.org/10.1109/EPTC.2004.1396684","url":null,"abstract":"Package reliability needs to be considered for the design of mixed flip-chip (FC)-wire bond (WB) stacked die BGA module with molded underfill (MUF). The success of the MUF application depends on its performance in thermal shock (TS) test and pressure cooker test (PCT). Mechanical properties (modulus and adhesion strength) of MUF after post mold cure (PMC), reflow and PCT are measured. Shear strength between die and MUF under various temperature and moisture conditions are also characterized. The results show that reflow process and PCT degrade the material properties and adhesion strength. Hygro-mechanical properties, i.e. coefficient of moisture expansion (CME) and saturated moisture concentration (Csat), are also measured. Based on the measured mechanical and moisture properties, a combined hygro-mechanical and thermo-mechanical stress modeling is performed on the FC-WB stacked die BGA package to compare three types of MUF materials at various temperatures (-40degC, 25degC, 121degC and 150degC) and PCT condition. It is observed that MUF-D3 material induces the lowest stresses on the die active surface. Die stresses induced by MUF with that of conventional mold compound and underfill materials are also compared. The analysis helps in material selection of MUF to enhance the die and package reliability of BGA module","PeriodicalId":370907,"journal":{"name":"Proceedings of 6th Electronics Packaging Technology Conference (EPTC 2004) (IEEE Cat. No.04EX971)","volume":"37 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-12-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114491167","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 2

Computational analyses on the effects of irregular conditions during accelerated thermal cycling tests on board level solder joint reliability 加速热循环试验中不规则条件对板级焊点可靠性影响的计算分析

Proceedings of 6th Electronics Packaging Technology Conference (EPTC 2004) (IEEE Cat. No.04EX971) Pub Date : 2004-12-08 DOI: 10.1109/EPTC.2004.1396663

D. Lau, S. Lee

{"title":"Computational analyses on the effects of irregular conditions during accelerated thermal cycling tests on board level solder joint reliability","authors":"D. Lau, S. Lee","doi":"10.1109/EPTC.2004.1396663","DOIUrl":"https://doi.org/10.1109/EPTC.2004.1396663","url":null,"abstract":"This study is intended to investigate the effects of irregular conditions on the board level solder joint reliability during accelerated thermal cycling tests. In a previous research, the thermal fatigue lives of PBGA solder joints have been estimated using a 2-dimensional finite element model. The computational results agreed very well with the experimental data. In the present study, with the previously developed finite element model, three cases of parametric studies are performed. In actual thermal cycling tests, it is usually quite difficult to achieve the ideal temperature profile in four linear segments as ramp-up, high temperature dwell, ramp-down, and low temperature dwell. The first case of the present study is to investigate the effect of imperfect temperature profile on the thermal fatigue life of PBGA solder joints. The second case under investigation is the effect of service interruption of the thermal cycling machine during the test. A certain time period of constant room temperature is inserted in the middle of the original temperature profile to simulate the breakdown of thermal cycling machine. In the third case, different starting temperatures are specified in order to simulate the effect of different stress free temperatures. The results of various computational analyses are compared and discussed in details","PeriodicalId":370907,"journal":{"name":"Proceedings of 6th Electronics Packaging Technology Conference (EPTC 2004) (IEEE Cat. No.04EX971)","volume":"40 323 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-12-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134041940","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 9

ECPR (electrochemical pattern replication): metal printing for advanced packaging applications ECPR(电化学图案复制):用于高级包装应用的金属印刷

Proceedings of 6th Electronics Packaging Technology Conference (EPTC 2004) (IEEE Cat. No.04EX971) Pub Date : 2004-12-08 DOI: 10.1109/EPTC.2004.1396621

P. Moller, M. Fredenberg, P. Nilsson, L. Karlsson, R. Pelzer, D. Lee

引用次数: 2

Design, manufacture and testing of a low-cost micro-channel cooling device 低成本微通道冷却装置的设计、制造与测试

Proceedings of 6th Electronics Packaging Technology Conference (EPTC 2004) (IEEE Cat. No.04EX971) Pub Date : 2004-12-08 DOI: 10.1109/EPTC.2004.1396671

A. J. Pang, M. Desmulliez, M. Leonard, R. Dhariwal, R. Reuben, A. Holmes, G. Hong, K. Pullen, F. Waldron, O. Slattery, M. Rencz, D. Emerson, R. Barber

引用次数: 8

A numerical study of fatigue life of copper column interconnections in wafer level packages 晶圆级封装中铜柱互连疲劳寿命的数值研究

Proceedings of 6th Electronics Packaging Technology Conference (EPTC 2004) (IEEE Cat. No.04EX971) Pub Date : 2004-12-08 DOI: 10.1109/EPTC.2004.1396626

Wei Sun, A. Tay, S. Vedantam

{"title":"A numerical study of fatigue life of copper column interconnections in wafer level packages","authors":"Wei Sun, A. Tay, S. Vedantam","doi":"10.1109/EPTC.2004.1396626","DOIUrl":"https://doi.org/10.1109/EPTC.2004.1396626","url":null,"abstract":"A copper column (CuC) interconnect technology is proposed in the nano wafer level packaging program as a chip-to-substrate interconnect solution for 20 mm by 20 mm package with 100 /spl mu/m pitch. Currently thermo-mechanical reliability of solder joint continues to be a major concern due to the CTE (coefficient of thermal expansion) mismatch between chip and substrate A FEA (finite element analysis) is carried out to estimate the fatigue life of the (critical) outermost corner CuC interconnect under thermal cycling. The commercial FEA software ABAQUS is used. Since a 3D finite element model constructed using 3D solid elements requires prohibitive computational resources, a macro-micro modeling approach which is feasible for handling simulation of large packages is used. This modified approach uses a global shell-and-beam model. By using shell-to-solid submodeling technique, a finely meshed submodel of the critical CuC interconnect can be analyzed. Maximum inelastic shear strain range is then extracted to estimate the solder joint fatigue life based on Solomon's correlation. In the current study, three CuCs with different heights are investigated. Fatigue lives of those three CuC interconnect are estimated and failure sites identified.","PeriodicalId":370907,"journal":{"name":"Proceedings of 6th Electronics Packaging Technology Conference (EPTC 2004) (IEEE Cat. No.04EX971)","volume":"27 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-12-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124716550","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 2

Examination of thermal performance of board-level QFP with unattached drop-in heat spreader 无附入式散热片板级QFP的热性能检验

Proceedings of 6th Electronics Packaging Technology Conference (EPTC 2004) (IEEE Cat. No.04EX971) Pub Date : 2004-12-08 DOI: 10.1109/EPTC.2004.1396573

T. Wang, Chang-Chi Lee, Y. Lai

引用次数: 4