发布求助
文献互助 智能选刊 最新文献

Proceedings of 6th Electronics Packaging Technology Conference (EPTC 2004) (IEEE Cat. No.04EX971)最新文献

筛选
英文 中文
Through wafer interconnection technologies for advanced electronic devices 通过晶圆互连技术实现先进的电子器件
Proceedings of 6th Electronics Packaging Technology Conference (EPTC 2004) (IEEE Cat. No.04EX971) Pub Date : 2004-12-08 DOI: 10.1109/EPTC.2004.1396566
M. de Samber, T. Nellissen, E. van Grunsven
{"title":"Through wafer interconnection technologies for advanced electronic devices","authors":"M. de Samber, T. Nellissen, E. van Grunsven","doi":"10.1109/EPTC.2004.1396566","DOIUrl":"https://doi.org/10.1109/EPTC.2004.1396566","url":null,"abstract":"There is a need for miniaturizing electronic components such as ICs and modules that are used in portable devices like cellular phones and PDAs. Miniaturization not only results in a reduced foot print of the components on the printed board but it can also have a positive effect on the device performance. The ultimate miniaturization is reached when packaging the component into a chip size package (CSP). To enable this, the bonding pads of ICs can be rerouted into, e.g., a ball grid array (BGA) configuration. For devices such as vertical discrete components and stacked dies planar rerouting is not sufficient. Introducing so-called through wafer interconnect enables addressing the back side and so these devices can be converted into CSPs. Although through wafer interconnect requires rather complicated technologies, wafer level processing (resulting in simultaneous fabrication of large number of packages) limits the additional packaging cost.","PeriodicalId":370907,"journal":{"name":"Proceedings of 6th Electronics Packaging Technology Conference (EPTC 2004) (IEEE Cat. No.04EX971)","volume":"62 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-12-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126618336","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 7
Transient analysis of board-level drop response of lead-free chip-scale packages with experimental verifications 无铅芯片级封装板级跌落响应的瞬态分析及实验验证
Proceedings of 6th Electronics Packaging Technology Conference (EPTC 2004) (IEEE Cat. No.04EX971) Pub Date : 2004-12-08 DOI: 10.1109/EPTC.2004.1396697
Chang-Lin Yeh, Y. Lai
{"title":"Transient analysis of board-level drop response of lead-free chip-scale packages with experimental verifications","authors":"Chang-Lin Yeh, Y. Lai","doi":"10.1109/EPTC.2004.1396697","DOIUrl":"https://doi.org/10.1109/EPTC.2004.1396697","url":null,"abstract":"Through the support excitation scheme, transient structural responses of a board-level chip-scale package subjected to the JEDEC drop test are analyzed using the implicit three-dimensional finite element analysis. Analyzed failure modes of the lead-free solder joints are verified with experimental observations. The effect of drop orientations on the reliability of the test vehicle is also examined.","PeriodicalId":370907,"journal":{"name":"Proceedings of 6th Electronics Packaging Technology Conference (EPTC 2004) (IEEE Cat. No.04EX971)","volume":"39 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-12-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127298635","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 31
Bump non-wet issue in large-die flip chip package with eutectic Sn/Pb solder bump and SOP substrate pad 采用共晶锡/铅焊料凸点和SOP衬底衬垫的大芯片倒装封装中的凸点不湿问题
Proceedings of 6th Electronics Packaging Technology Conference (EPTC 2004) (IEEE Cat. No.04EX971) Pub Date : 2004-12-08 DOI: 10.1109/EPTC.2004.1396648
Z. Xiong, Ho Pei Sze, K. H. Chua
{"title":"Bump non-wet issue in large-die flip chip package with eutectic Sn/Pb solder bump and SOP substrate pad","authors":"Z. Xiong, Ho Pei Sze, K. H. Chua","doi":"10.1109/EPTC.2004.1396648","DOIUrl":"https://doi.org/10.1109/EPTC.2004.1396648","url":null,"abstract":"This paper describes a study on non-wet issue encountered in flip chip assembly process of high-density flip chip ball grid array (FCBGA) packages with eutectic Sn/Pb solder interconnects. A nonwet occurrence is more obvious in large-die flip chip (die size >16mm) with high I/O counts (>1000). Thermal-mechanical mismatch between die and substrate shows a role in affecting soldering condition of the die solder bump and substrate SOP. Positive evaluation results, involving: 1) new flux material with increased percentage of solid content or modified activator and 2) plasma treatment on substrate prior to FC assembly, indicate that a more effective approach is needed to improve bump solderability in large die flip chip devices","PeriodicalId":370907,"journal":{"name":"Proceedings of 6th Electronics Packaging Technology Conference (EPTC 2004) (IEEE Cat. No.04EX971)","volume":"10 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-12-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121871406","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 10
The development of a test vehicle for applications in ambient electronic systems using very thin flexible substrate 开发一种测试车辆，用于使用非常薄的柔性衬底的环境电子系统
Proceedings of 6th Electronics Packaging Technology Conference (EPTC 2004) (IEEE Cat. No.04EX971) Pub Date : 2004-12-08 DOI: 10.1109/EPTC.2004.1396636
B. Majeed, K. Delaney, J. Barton, K. Razeeb, N. MacCarthy, C. O'Mathúna
{"title":"The development of a test vehicle for applications in ambient electronic systems using very thin flexible substrate","authors":"B. Majeed, K. Delaney, J. Barton, K. Razeeb, N. MacCarthy, C. O'Mathúna","doi":"10.1109/EPTC.2004.1396636","DOIUrl":"https://doi.org/10.1109/EPTC.2004.1396636","url":null,"abstract":"In this work the development and characterisation of a very thin flexible substrate, with thickness ranging from 3 microns to 25 microns, was presented. The work analyses the stress generated in thin flexible substrate and determines the critical thickness to avoid wrinkling in the substrate. This substrate is then used to package test chips into a highly miniaturised 3D module. The 3D module consists of 4 IC's each having thickness of 50 microns and total module is approximately 450 microns in thickness and with a footprint of 18/spl times/7mm/sup 2/. This module is being developed as a technological demonstrator for the \"I-Seed\". The I-seed is an NMRC envisioned distributed autonomous micromodule that would interact, respond and learn from its surroundings making integration of engineering, computer science and human intelligence a reality.","PeriodicalId":370907,"journal":{"name":"Proceedings of 6th Electronics Packaging Technology Conference (EPTC 2004) (IEEE Cat. No.04EX971)","volume":"67 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-12-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121653711","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Can nanoindentation help to determine the local mechanical properties of microelectronic materials? a state-of-the-art review 纳米压痕能帮助确定微电子材料的局部力学性能吗?最先进的评论
Proceedings of 6th Electronics Packaging Technology Conference (EPTC 2004) (IEEE Cat. No.04EX971) Pub Date : 2004-12-08 DOI: 10.1109/EPTC.2004.1396652
H. Albrecht, T. Hannach, A. Hase, A. Juritza, K. Műller, W. Muller
{"title":"Can nanoindentation help to determine the local mechanical properties of microelectronic materials? a state-of-the-art review","authors":"H. Albrecht, T. Hannach, A. Hase, A. Juritza, K. Műller, W. Muller","doi":"10.1109/EPTC.2004.1396652","DOIUrl":"https://doi.org/10.1109/EPTC.2004.1396652","url":null,"abstract":"We investigate the mechanical properties of intermetallic phases in microelectronic structures with the help of nanoindentation. Moreover, we shall try to answer the question as to whether nanoindentation can be used to quantify the growth of intermetallic phases, at least at the interface of a solder connection. Different specimens and treatments (such as reflow processes and subsequent aging) have been analyzed. The results of these experiments serve as reference values for FE-simulations which are also discussed.","PeriodicalId":370907,"journal":{"name":"Proceedings of 6th Electronics Packaging Technology Conference (EPTC 2004) (IEEE Cat. No.04EX971)","volume":"28 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-12-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130587246","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
Package optimization of a stacked die flip chip based test package 基于叠片倒装芯片的测试封装优化
Proceedings of 6th Electronics Packaging Technology Conference (EPTC 2004) (IEEE Cat. No.04EX971) Pub Date : 2004-12-08 DOI: 10.1109/EPTC.2004.1396676
J. Pohl, M. Graml, Peter Strobel, Rainer Steiner, Klaus Pressel, S. Stoeckl, Gerald Ofner, Charles Lee
{"title":"Package optimization of a stacked die flip chip based test package","authors":"J. Pohl, M. Graml, Peter Strobel, Rainer Steiner, Klaus Pressel, S. Stoeckl, Gerald Ofner, Charles Lee","doi":"10.1109/EPTC.2004.1396676","DOIUrl":"https://doi.org/10.1109/EPTC.2004.1396676","url":null,"abstract":"We report a case study for the optimization of a flip chip based stacked die array test package. We demonstrate the importance of package substrate design and substrate thickness on the processibility and package warpage control. We found that for thin substrates copper balancing of the top and bottom die is crucial. We show the impact of flip chip die thickness and substrate thickness on the die attach of the top die(s) in the stack. Investigations on different top die attach alternatives show that tape die attach can have advantages. We demonstrate the importance of the vertical stack structure (i.e. flip chip thickness) and material selection (i.e. mold compound) on the overall warpage control of the package. The results show that even small changes in the package structure can have large impact on the warpage characteristics of the stacked die package","PeriodicalId":370907,"journal":{"name":"Proceedings of 6th Electronics Packaging Technology Conference (EPTC 2004) (IEEE Cat. No.04EX971)","volume":"40 3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-12-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130538769","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
Controlling simultaneous switching noise with built-in decoupling capacitors 内置去耦电容控制同步开关噪声
Proceedings of 6th Electronics Packaging Technology Conference (EPTC 2004) (IEEE Cat. No.04EX971) Pub Date : 2004-12-08 DOI: 10.1109/EPTC.2004.1396689
Yoshiyuki Kosaka, Narimasa Takahashi, Shin Suminaga
{"title":"Controlling simultaneous switching noise with built-in decoupling capacitors","authors":"Yoshiyuki Kosaka, Narimasa Takahashi, Shin Suminaga","doi":"10.1109/EPTC.2004.1396689","DOIUrl":"https://doi.org/10.1109/EPTC.2004.1396689","url":null,"abstract":"This work describes two modeling methodologies to evaluate simultaneous switching noise (SSN) for a four layers printed circuit board (PCB). The first modeling was done using Ansoft Q3D to extract related loop inductances for 16 simultaneous switching outputs (SSO) and estimate the noise voltage. The second modeling was done using Sigrity SPEED2000 to evaluate 128 SSOs and their design practice to keep the noise voltage within 5% of the operational voltage. Simulation results for both tools were also compared and discussed.","PeriodicalId":370907,"journal":{"name":"Proceedings of 6th Electronics Packaging Technology Conference (EPTC 2004) (IEEE Cat. No.04EX971)","volume":"51 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-12-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115050820","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
High precision passive alignment flip chip assembly using self-alignment and micromechanical stops 采用自对准和微机械停止的高精度被动对准倒装芯片组装
Proceedings of 6th Electronics Packaging Technology Conference (EPTC 2004) (IEEE Cat. No.04EX971) Pub Date : 2004-12-08 DOI: 10.1109/EPTC.2004.1396639
M. Hutter, H. Opperrnann, G. Engelmann, H. Reichl
{"title":"High precision passive alignment flip chip assembly using self-alignment and micromechanical stops","authors":"M. Hutter, H. Opperrnann, G. Engelmann, H. Reichl","doi":"10.1109/EPTC.2004.1396639","DOIUrl":"https://doi.org/10.1109/EPTC.2004.1396639","url":null,"abstract":"The implementation of passive alignment in optoelectronics packaging is still a challenge. Flip chip assembly of single mode laser diodes requires a post bond alignment accuracy of less than 1 /spl mu/m. A low cost approach to achieve such high precision alignment is using the self-alignment mechanism in combination with micromechanical stops. In order to prove that this approach is feasible test vehicles were designed and fabricated. This work presents the concept of passive alignment pursued, the experimental setup and results thereof. The design of the test vehicles is described including the bump design as well as bumping and flip chip assembly.","PeriodicalId":370907,"journal":{"name":"Proceedings of 6th Electronics Packaging Technology Conference (EPTC 2004) (IEEE Cat. No.04EX971)","volume":"246 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-12-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115009396","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
Through-substrate trenches for RF isolation in wafer-level chip-scale package 在晶圆级芯片级封装中用于射频隔离的穿过基板沟槽
Proceedings of 6th Electronics Packaging Technology Conference (EPTC 2004) (IEEE Cat. No.04EX971) Pub Date : 2004-12-08 DOI: 10.1109/EPTC.2004.1396569
S. Sinaga, A. Polyakov, M. Bartek, J. Burghartz
{"title":"Through-substrate trenches for RF isolation in wafer-level chip-scale package","authors":"S. Sinaga, A. Polyakov, M. Bartek, J. Burghartz","doi":"10.1109/EPTC.2004.1396569","DOIUrl":"https://doi.org/10.1109/EPTC.2004.1396569","url":null,"abstract":"The wafer-level chip-scale packaging (WLCSP) concept offers a lot of new possibilities. Not only is the package size smaller, but also features to improve the performance can be easily realized. It is widely known that the radio frequency integrated circuit (RFIC) suffers from substrate coupling due to its electrically conducting substrate. The downscaling of RFIC and the increasing operating frequency make the substrate coupling even more problematic. This paper proposes through-substrate trench as schemes to suppress the substrate coupling. A through-substrate trench can easily be realized using WLCSP concept without any drawback in mechanical reliability. Topologies for equivalent circuit modeling approach are also introduced in this work.","PeriodicalId":370907,"journal":{"name":"Proceedings of 6th Electronics Packaging Technology Conference (EPTC 2004) (IEEE Cat. No.04EX971)","volume":"246 6‐9","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-12-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132442708","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
A novel WLCSP technology with high reliability, low cost and ease of fabrication 一种高可靠性、低成本、易于制造的新型WLCSP技术
Proceedings of 6th Electronics Packaging Technology Conference (EPTC 2004) (IEEE Cat. No.04EX971) Pub Date : 2004-12-08 DOI: 10.1109/EPTC.2004.1396568
Shu-Ming Chang, Chin-Yuan Cheng, Li-Cheng Shen, Yu-Jiau Hwang, Yu-Fang Chen, Jeng-Dar Ko, Hsun Hu, Kuo-Chuan Chen, Chich-Yuan Chang, K. Chiang
{"title":"A novel WLCSP technology with high reliability, low cost and ease of fabrication","authors":"Shu-Ming Chang, Chin-Yuan Cheng, Li-Cheng Shen, Yu-Jiau Hwang, Yu-Fang Chen, Jeng-Dar Ko, Hsun Hu, Kuo-Chuan Chen, Chich-Yuan Chang, K. Chiang","doi":"10.1109/EPTC.2004.1396568","DOIUrl":"https://doi.org/10.1109/EPTC.2004.1396568","url":null,"abstract":"Wafer level chip scale packaging (WLCSP) has some advantages, such as real die size packaging, high electrical performance and low manufacturing cost. However, because the mechanical reliability of a large die can not be guaranteed due to the CTE (coefficient of thermal expansion) mismatch between silicon and organic PCB (printed circuit board), WLCSP technology is still not fully accepted. We have developed a new SJP-WLCSP (solder joint protection-WLCSP) structure with a delamination layer interposed between the top layer of the chip and the bottom insulating layer of the metal redistribution traces. The stress on the solder joints can be released by the cracks forming in the delamination layer, which protects the solder joints from cracking. Since the cracking of the delamination layer is irrelevant to the electrical circuits of the packaging, the packaged IC (integrated circuits) device remains functional. One of the possibilities for processing the SJP-WLCSP was implemented and validated successfully in the SiLK-wafer samples. The board level packaging samples, using the daisy chain resistance measurement passed 1000 cycles of the temperature cycling testing.","PeriodicalId":370907,"journal":{"name":"Proceedings of 6th Electronics Packaging Technology Conference (EPTC 2004) (IEEE Cat. No.04EX971)","volume":"225 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-12-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130695364","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
首页 上一页 下一页 尾页
0
×
引用
GB/T 7714-2015
复制
MLA
复制
APA
复制
导出至
BibTeX EndNote RefMan NoteFirst NoteExpress
×
提示
您的信息不完整，为了账户安全，请先补充。
现在去补充
×
提示
您因"违规操作"
具体请查看互助需知
我知道了
×
提示
现在去查看 取消
×
提示
确定
请完成安全验证×
相关产品
×
本文献相关产品
联系我们：info@booksci.cn Book学术提供免费学术资源搜索服务，方便国内外学者检索中英文文献。致力于提供最便捷和优质的服务体验。 Copyright © 2023 布克学术 All rights reserved.
京ICP备2023020795号-1
ghs 京公网安备 11010802042870号
Book学术文献互助
Book学术文献互助群
群 号：481959085
Book学术官方微信