Y. Kohara, R. Usui, A. Nishida, H. Mizuhara, T. Nakarrwra, S. Mori, N. Takakusaki, Y. Igarashi, Y. Inoue
{"title":"Improvement in moisture resistance of thin SiP utilizing the plasma treatment of resin surface","authors":"Y. Kohara, R. Usui, A. Nishida, H. Mizuhara, T. Nakarrwra, S. Mori, N. Takakusaki, Y. Igarashi, Y. Inoue","doi":"10.1109/EPTC.2004.1396593","DOIUrl":"https://doi.org/10.1109/EPTC.2004.1396593","url":null,"abstract":"In downsizing the SiP (system in package) thickness, moisture resistance reliability has been a serious problem, because of the weak adhesion property of the interface between the interposer and mold resin (Alpern et al., 2003). Also, the SiP requires more heat resistance because of the high reflow temperature in the lead free solder process. In this work, we have improved the adhesion property with a new plasma treatment technology. It is argon or argon-oxygen mixture plasma treatment of PSR (photo solder resist) surface composed of Cardo polymer which has excellent heat resistance compared to the conventional PSR. The plasma treatment improved the adhesion property of the interface between this PSR and mold resin. As a result, the moisture resistance reliability of the module was improved. SEM (scanning electron microscope) images of the PSR surface treated with plasma showed the generation of projections caused the anchor effect. XPS (X-ray photoelectron spectroscopy) spectra indicated that the plasma treatment changed the chemical combined states of the PSR surface. From these results, both the anchor effect and the chemical bond effect increased the adhesion property at the PSR/mold resin interface. Therefore, with the adhesion improvement from the plasma treatment process and by adopting a highly heat resistant cardo polymer PSR it is possible to miniaturize a fine moisture-resistant and heat-resistant SiP","PeriodicalId":370907,"journal":{"name":"Proceedings of 6th Electronics Packaging Technology Conference (EPTC 2004) (IEEE Cat. No.04EX971)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-12-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129339715","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
C. Yoon, J. Landeros, H. Goh, A. Teh, J. Chee, C. Loke, S. Mahadevan
{"title":"Substrate design optimization for high performance small form factor flip chip ball grid array (FCBGA) packages","authors":"C. Yoon, J. Landeros, H. Goh, A. Teh, J. Chee, C. Loke, S. Mahadevan","doi":"10.1109/EPTC.2004.1396635","DOIUrl":"https://doi.org/10.1109/EPTC.2004.1396635","url":null,"abstract":"This work summarizes the multiple design and development activities within Intel to optimize the real estate for FCBGA packaging technology. The advantages made are part of the cost saving solutions to enable high performance small form factor flip chip ball grid array (FCBGA) substrate. Key focus areas include challenges in enabling ultra mini 0402/0201 die side capacitor (DSC), optimizing transfer media or material handling system, optimizing assembly and test tooling design for smaller and cheaper substrate design.","PeriodicalId":370907,"journal":{"name":"Proceedings of 6th Electronics Packaging Technology Conference (EPTC 2004) (IEEE Cat. No.04EX971)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-12-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129618525","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Thermal fatigue reliability analysis for PBGA with Sn-3.8Ag-0.7Cu solder joints","authors":"F. Che, J. Pang","doi":"10.1109/EPTC.2004.1396715","DOIUrl":"https://doi.org/10.1109/EPTC.2004.1396715","url":null,"abstract":"In this work, thermal cycling reliability test and analysis for PBGA components with Sn-3.8Ag-0.7Cu solder joints were investigated. Based on test results, a two-parameter Weibull distribution model was used to determine the mean time to failure (MTTF) of PBGA components. The MTTF was used for validation of finite element analysis (FEA) results. FEA analysis using quarter model and submodeling method was implemented to study stress strain behavior of Sn-3.8Ag-0.7Cu lead free solder joints considering three thermal cycles. In FEA analysis, two different solder joint material constitutive models, viscoplastic Anand's model and elastic-plastic-creep model, and two different fatigue life prediction models, energy based and strain based fatigue life model, were used for comparison. Volume averaged method was used for extracting fatigue life prediction parameter. Traditional whole interface layer elements averaged method overestimates the fatigue life of solder joint due to lower energy or strain used in fatigue life model. In this paper, new averaging volume of outermost ring elements was proposed. It was shown that outermost ring elements averaging method gave better result compared to MTTF. Thermal cycling and thermal shock loads were simulated in FEA analysis to study the temperature ramp rate effects on fatigue life.","PeriodicalId":370907,"journal":{"name":"Proceedings of 6th Electronics Packaging Technology Conference (EPTC 2004) (IEEE Cat. No.04EX971)","volume":"61 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-12-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127508860","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Saraswati, E. Theint, D. Stephan, F. Wulff, C. Breach, D. Calpito
{"title":"Looping behaviour of gold ballbonding wire","authors":"Saraswati, E. Theint, D. Stephan, F. Wulff, C. Breach, D. Calpito","doi":"10.1109/EPTC.2004.1396702","DOIUrl":"https://doi.org/10.1109/EPTC.2004.1396702","url":null,"abstract":"Gold ballbonding is an enabling technology in electronics packaging that accounts for around 90% of the world demand for packaged IC's. Thinner IC packaging demands lower wire loops and the stacked dies used for example in mobile telecommunications applications require a range of loop heights from very high to very low. In addition, multi-tier wirebonding also demands ultra low loop profile for its application. The lowest achievable loop heights are physically constrained by the wire dimensions and the plastic deformation behaviour of the wire. Ultra low loops result in extensive plastic deformation in the heat affected zone (HAZ). This paper examines the correlation between the wire properties (break load, modulus, hardness, grain size, HAZ length) and looping performance. The springback height of the lifted ball due to tension in the wire from bonding, and how it affects the looping behaviour is also discussed.","PeriodicalId":370907,"journal":{"name":"Proceedings of 6th Electronics Packaging Technology Conference (EPTC 2004) (IEEE Cat. No.04EX971)","volume":"28 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-12-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116552949","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Marc P. Y. Desmulliez, Robert W. Kay, S. Stoyanov, Chris Bailey
{"title":"Stencil printing at sub-100 microns pitch","authors":"Marc P. Y. Desmulliez, Robert W. Kay, S. Stoyanov, Chris Bailey","doi":"10.1109/EPTC.2004.1396633","DOIUrl":"https://doi.org/10.1109/EPTC.2004.1396633","url":null,"abstract":"This article presents the latest print results at less than 100 microns pitch obtained in stencil printing type 6 and 7 lead-free solder pastes and conductive adhesives. The advantages of the microengineered stencil arc presented and compared with other bonding technologies. Characterisation of the print deposits is presented and future applications of stencil printing are described.","PeriodicalId":370907,"journal":{"name":"Proceedings of 6th Electronics Packaging Technology Conference (EPTC 2004) (IEEE Cat. No.04EX971)","volume":"49 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-12-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131001884","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
S. Chong, S. Ting, T. Y. Meng, C. T. Chong, S. Sampath, H. W. Yin, S. Lim, Cheng Chek Kweng
{"title":"Reliability assessment of high density fine pitch lead-free flip chip package","authors":"S. Chong, S. Ting, T. Y. Meng, C. T. Chong, S. Sampath, H. W. Yin, S. Lim, Cheng Chek Kweng","doi":"10.1109/EPTC.2004.1396647","DOIUrl":"https://doi.org/10.1109/EPTC.2004.1396647","url":null,"abstract":"It is now possible to build high performance integrated circuit (IC) due to the recent advancement in the chip fabrication process. To meet the high performance IC, the chip's input/output (I/O) counts have to increase and this resulted in fine pitch and large IC. In addition, there is a drive towards using environmental-friendly material. The lead free solder, fine pitch, large die and organic substrate are features commonly found in the high performance IC package. However, these features pose a significance challenge to the package reliability in terms of moisture sensitivity test and temperature cycling performance. The concern arises due to the compatibility issues involving the underfill, flux, passivation material and the under-bump metallization (UBM). However, material compatability is only part of the reasons. Others include Pb free solder, large die, fine pitch, organic substrate which are not addressed in This work. The objectives of this work are optimizing of the assembly process and identifying suitable material set for a reliable high-density fine pitch lead free flip chip organic package.","PeriodicalId":370907,"journal":{"name":"Proceedings of 6th Electronics Packaging Technology Conference (EPTC 2004) (IEEE Cat. No.04EX971)","volume":"6 4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-12-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134094682","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
A. Priyadarshi, P. Ramana, C. J. Leo, S. Mhaisalkar, V. Kripesh
{"title":"Link simulation of four channel CWDM transceiver modules","authors":"A. Priyadarshi, P. Ramana, C. J. Leo, S. Mhaisalkar, V. Kripesh","doi":"10.1109/EPTC.2004.1396711","DOIUrl":"https://doi.org/10.1109/EPTC.2004.1396711","url":null,"abstract":"Optical communication systems are extremely complex and difficult to analyze. It is often hard to predict the effect of various characteristics of the devices used on the signal fidelity in a fiber optic link. This work involves simulation of 2.5 Gigabits per second (Gbps) coarse wavelength division multiplexing (CWDM) transceiver for end-to-end link performance. Simulation software is available commercially which can realistically model an optical link. Such simulation helps in analyzing the module under development and predicts the performance for a given link distance and the simulation output helps eliminating any likely performance degradation before realizing the actual hardware. The objective of the fiber optic link is to transport data or communication signals reliably over a longer distance. The desired Q factor is approximately 7 and the desired bit error rate (BER) is approximately 10/sup -12/. The simulation objective is to ensure that the received pulses are of appropriate shape and of sufficient intensity, with minimized loss due to noise or attenuation, and to remove distortion present in the signal. The Q factor and BER obtained from either the eye diagram analyzer or the BER analyzer are used to analyze the degradation of the signal at the receiver components.","PeriodicalId":370907,"journal":{"name":"Proceedings of 6th Electronics Packaging Technology Conference (EPTC 2004) (IEEE Cat. No.04EX971)","volume":"13 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-12-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134582602","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Considerations for a robust moisture performance of a flip chip in package for lead-free soldering","authors":"G. Ofner, K. L. Chua, M. Teo, C. Lee","doi":"10.1109/EPTC.2004.1396607","DOIUrl":"https://doi.org/10.1109/EPTC.2004.1396607","url":null,"abstract":"This work provides a comprehensive study on several approaches to obtain a robust lead-free flip chip package. The influence of materials, chip passivation, package configuration and cleaning processes were investigated to provide insights on the effectiveness of each approach to improve the moisture sensitivity level (MSL) performance. Results showed that the underfill/flux compatibility to the chip passivation has a strong influence on the MSL performance. Furthermore, it was observed that the unmolded version generally has a better MSL performance than the molded flip chip in package (FCIP) for a given material combination. However, there is no strong correlation between MSL performance and material properties. The plasma cleaning and defluxing processes were introduced to assess any potential improvement in MSL performance. Based on the results, plasma cleaning was found to be effective in improving the MSL performance. Defluxing evaluation showed potential for MSL performance improvement provided the defluxing process is well controlled. It is also worth noting that with the right underfill/flux/passivation combination, plasma cleaning may not be necessary to achieve the same MSL performance. In summary, this paper has emphasized the importance of mold compound/underfill/flux/passivation compatibility and the effectiveness of an optimized plasma cleaning or defluxing process to improve MSL performance. This study has also sucessfully demonstrated that MSL 1 performance can be achieved with the right choice of materials combination without additional cleaning processes.","PeriodicalId":370907,"journal":{"name":"Proceedings of 6th Electronics Packaging Technology Conference (EPTC 2004) (IEEE Cat. No.04EX971)","volume":"66 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-12-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133866749","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
P. Hegde, K. N. Seetharamu, P. Aswatha Narayana, Zulkifly Abdullah
{"title":"Thermal analysis of single layer counter flow heat sinks with two phase flow","authors":"P. Hegde, K. N. Seetharamu, P. Aswatha Narayana, Zulkifly Abdullah","doi":"10.1109/EPTC.2004.1396670","DOIUrl":"https://doi.org/10.1109/EPTC.2004.1396670","url":null,"abstract":"The thermal performance of single layer counter-flow (SLCF) microchannel heat sinks with two-phase flow have been analyzed using the finite element method. Parameters such as the thermal resistance, pressure drop and the temperature distribution in SLCF heat sinks with two-phase flow have been determined and compared with those for the single layer parallel flow (SLPF) heat sinks with two-phase flow. It is observed that two-phase flow in the micro-channel heat sinks generally yield low thermal resistance and better temperature uniformity in the stream-wise direction. It is also observed that the thermal performance of the SLCF microchannel heat sinks are better especially at higher base heat fluxes compared to the SLPF heat sinks working under similar conditions","PeriodicalId":370907,"journal":{"name":"Proceedings of 6th Electronics Packaging Technology Conference (EPTC 2004) (IEEE Cat. No.04EX971)","volume":"21 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-12-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115956042","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
V. N. Sekhar, V. Srinivasarao, R. Jayaganthan, K. Mohankumar, A. Tay
{"title":"A study on the mechanical behavior of the sputtered nickel thin films for UBM applications","authors":"V. N. Sekhar, V. Srinivasarao, R. Jayaganthan, K. Mohankumar, A. Tay","doi":"10.1109/EPTC.2004.1396680","DOIUrl":"https://doi.org/10.1109/EPTC.2004.1396680","url":null,"abstract":"Nickel films of different thicknesses of 0.5 and 0.8 /spl mu/m were deposited by DC magnetron sputtering on the adhesion promoting Ta layer deposited on the silicon (100) wafer. The sputtering conditions used were 4 /spl times/ 10/sup -6/ base pressure; 3 /spl times/ 10/sup -1/ working pressure; 4 kW sputter power for 8 inch targets. The films were annealed in vacuum at temperature 200/spl deg/C and their elastic modulus and hardness were measured by nanoindentation technique (hysitron triboscope). Different load rates were used when indenting the samples. The influence of thickness and annealing temperature on the mechanical behaviour of nickel thin films is explored in the present work.","PeriodicalId":370907,"journal":{"name":"Proceedings of 6th Electronics Packaging Technology Conference (EPTC 2004) (IEEE Cat. No.04EX971)","volume":"13 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-12-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114424190","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}