Substrate design optimization for high performance small form factor flip chip ball grid array (FCBGA) packages

Proceedings of 6th Electronics Packaging Technology Conference (EPTC 2004) (IEEE Cat. No.04EX971) Pub Date : 2004-12-08 DOI:10.1109/EPTC.2004.1396635

C. Yoon, J. Landeros, H. Goh, A. Teh, J. Chee, C. Loke, S. Mahadevan

引用次数: 1

Abstract

This work summarizes the multiple design and development activities within Intel to optimize the real estate for FCBGA packaging technology. The advantages made are part of the cost saving solutions to enable high performance small form factor flip chip ball grid array (FCBGA) substrate. Key focus areas include challenges in enabling ultra mini 0402/0201 die side capacitor (DSC), optimizing transfer media or material handling system, optimizing assembly and test tooling design for smaller and cheaper substrate design.

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高性能小尺寸倒装芯片球栅阵列(FCBGA)封装的基板设计优化

这项工作总结了英特尔内部的多种设计和开发活动，以优化FCBGA封装技术的房地产。所取得的优势是实现高性能小尺寸倒装芯片球栅阵列(FCBGA)基板的成本节约解决方案的一部分。重点关注领域包括实现超小型0402/0201模侧电容器(DSC)的挑战，优化传输介质或材料处理系统，优化组装和测试工具设计，以实现更小、更便宜的基板设计。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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来源期刊

Proceedings of 6th Electronics Packaging Technology Conference (EPTC 2004) (IEEE Cat. No.04EX971)

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