Through-substrate trenches for RF isolation in wafer-level chip-scale package

Abstract

The wafer-level chip-scale packaging (WLCSP) concept offers a lot of new possibilities. Not only is the package size smaller, but also features to improve the performance can be easily realized. It is widely known that the radio frequency integrated circuit (RFIC) suffers from substrate coupling due to its electrically conducting substrate. The downscaling of RFIC and the increasing operating frequency make the substrate coupling even more problematic. This paper proposes through-substrate trench as schemes to suppress the substrate coupling. A through-substrate trench can easily be realized using WLCSP concept without any drawback in mechanical reliability. Topologies for equivalent circuit modeling approach are also introduced in this work.